Ethernet PHY & High-Speed SerDes (PCS / FEC / 802.3) Interview Prep
Ethernet PHY interview prep: the IEEE 802.3 PCS/PMA/PMD stack, RS-FEC (KR4/KP4), PAM4 lanes, PMD naming for 100G/400G/800G, alignment markers, and Clause 73/72 link training.
Quick answer
The Ethernet PHY is the physical layer defined by IEEE 802.3 that turns MAC frames into signals on copper or fiber, built from a stack of standardized sublayers and high-speed SerDes lanes.
Ethernet PHY questions separate candidates who have actually brought up a high-speed link from those who have only read about networking.
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Wireless / RF / hardware engineering
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Key points
- IEEE 802.3 splits the Ethernet PHY into PCS (coding/scrambling/FEC/lane distribution), PMA (SerDes: serialize, mux, clock recovery), and PMD (medium-specific TX/RX).
- PMD names are systematic: rate + BASE + medium letter (K/C/T copper; S/D/F/L/E optical) + lane count — e.g. 100GBASE-KR4, 400GBASE-DR4, 800GBASE-DR8.
- High-speed Ethernet mandates Reed-Solomon FEC, specified per PMD: RS(528,514) = KR4 (lighter, common on NRZ), RS(544,514) = KP4 (stronger, the PAM4 workhorse); BER is specified both pre-FEC and post-FEC.
- PAM4 carries 2 bits/symbol so a 100G lane runs ~53 Gbaud (Nyquist ~26.5 GHz vs ~50 GHz for 100G NRZ), at the cost of ~9.5 dB less eye amplitude (the 20·log10(3) level-spacing penalty); it requires stronger equalization plus mandatory KP4 FEC.
- The PCS distributes 64b/66b-coded data across PCS lanes with periodic alignment markers so the receiver can deskew and reassemble across any PMD lane count.
- Copper PMDs (KR/KP/CR) use Clause 73 auto-negotiation plus link training to tune the remote TX FFE taps; optical PMDs use DSP-based adaptive equalization.
- Ethernet (802.3, framed/packet-switched) shares SerDes physics with PCIe but differs in stack; TSN (802.1) sits above the MAC and does not change the PHY.
What it is
The Ethernet PHY is the physical layer defined by IEEE 802.3 that turns MAC frames into signals on copper or fiber, built from a stack of standardized sublayers and high-speed SerDes lanes. Below the MAC, the Physical Coding Sublayer (PCS) handles 64b/66b line coding, scrambling, lane distribution with alignment markers, and — at 25G and above — Reed-Solomon FEC; the Physical Medium Attachment (PMA) is the SerDes that serializes, muxes, and recovers the clock (see /topics/serdes-design-fundamentals); and the Physical Medium Dependent (PMD) sublayer is the medium-specific transmitter and receiver for backplane, twinax, twisted pair, or optics. What makes the Ethernet PHY distinct from a generic serial link is the standards machinery layered on top of the SerDes: a systematic PMD naming scheme (100GBASE-KR4, 400GBASE-DR4, 800GBASE-DR8), mandatory FEC variants (KR4 vs KP4), PAM4 signaling at 50G and 100G per lane, and Clause 73/72 auto-negotiation and link training on copper. Ports at 100G, 400G, and 800G are assembled by aggregating these lanes and striping data across them. Strong PHY engineers can map a rate to its lanes, medium, FEC, and signaling, and they keep the PHY layer cleanly separate from the MAC and from 802.1 features like TSN (see /topics/time-sensitive-networking-tsn). This page is scoped to that PHY layer — not switching, routing, or enterprise networking.
Why interviewers ask
Ethernet PHY questions separate candidates who have actually brought up a high-speed link from those who have only read about networking. Hardware, SerDes, and SI/PI engineers all touch this layer, so interviewers use it to test whether you understand the standardized stack — PCS, PMA, PMD — and not just the abstract idea of a serial link. A precise answer reads a PMD name correctly, knows which FEC a given rate uses, explains why PAM4 forced KP4 FEC into the link budget, and can describe how the PCS distributes data across lanes and deskews them. Interviewers also probe the boundary discipline: where does the PHY stop and the MAC begin, how is Ethernet different from PCIe (see /topics/pcie-gen5-gen6-explained) even though both use the same SerDes, and where does TSN sit in the stack. Because these links live or die on channel quality, the conversation usually crosses into signal integrity — insertion loss, equalization, eye margin (see /topics/signal-integrity-fundamentals) — and the power delivery the transceivers need (see /topics/power-integrity-and-pdn-design). The signal is layered, standards-aware reasoning, not vocabulary recall.
Common mistakes
The most common mistake is treating Ethernet PHY as if it were corporate networking — talking about switches, VLANs, or routing instead of the 802.3 physical layer. A second is misreading PMD names: confusing the lane count with the rate, or not knowing that the medium letter (K for backplane, C for cable, D/L/S for optics) and the trailing digit encode reach and lane count. A third is calling FEC optional; at 25G and up it is mandatory and budgeted into the link, and candidates who cannot distinguish KR4 (RS(528,514), NRZ) from KP4 (RS(544,514), PAM4) reveal a shallow model. A fourth is conflating pre-FEC and post-FEC BER — the raw channel BER is high by design and FEC pulls it under 1e-12. A fifth is assuming copper Ethernet transmitters are statically tuned, missing that Clause 73 auto-negotiation and link training adapt the remote TX taps over the live link. Finally, weaker candidates blur layers — attributing TSN or framing to the PHY, or assuming Ethernet and PCIe are interchangeable because they share SerDes — when the discriminating answer keeps PHY, MAC, and the 802.1 control plane distinct.
Frequently asked questions
- What are the PCS, PMA, and PMD sublayers in the Ethernet PHY?
- IEEE 802.3 decomposes the PHY into stacked sublayers below the MAC. The Physical Coding Sublayer (PCS) does line coding, scrambling, lane distribution, and — at 25G and above — Reed-Solomon FEC; for high-speed Ethernet it uses 64b/66b encoding and a block-distribution scheme (PCS lanes) so the bitstream can be striped across multiple electrical or optical lanes and realigned with alignment markers. The Physical Medium Attachment (PMA) handles serialization/deserialization, bit muxing between PCS lanes and physical lanes, and clock recovery — this is the SerDes proper (see /topics/serdes-design-fundamentals). The Physical Medium Dependent (PMD) sublayer is the actual transmitter and receiver for one medium: copper backplane, twinax cable, or optics. The MAC talks to the PCS through a media-independent interface (xMII / xGMII family); the PMD talks to the channel. Naming a PMD precisely is a common interview signal.
- How do you read a PMD name like 400GBASE-DR4 or 100GBASE-KR4?
- The 802.3 PMD nomenclature is systematic: the leading number is the aggregate data rate (100G, 400G, 800G), BASE means baseband signaling, the letter encodes the medium, and the trailing digit is the lane count. Medium letters include K for copper backplane, C for twinax copper cable, T for twisted pair, and the optical letters S (short-reach multimode), D (~500 m single-mode, the per-lane DR family), F (~2 km), L (~10 km), and E (~40 km) — nominal reaches that vary by PMD. So 100GBASE-KR4 is 100G over a copper backplane on four lanes (25G each), 400GBASE-DR4 is 400G over single-mode fiber on four 100G lanes, and 800GBASE-DR8 is 800G over eight 100G lanes. Reading these correctly tells an interviewer you understand rate, medium, reach, and lane structure at once.
- Why does high-speed Ethernet require Reed-Solomon FEC, and what is KR4 vs KP4?
- At 25G per lane and beyond, the raw pre-FEC bit error rate of a lossy channel is far too high to meet the operational target (1e-12 or better), and PAM4 makes it worse by stacking three eyes into the same amplitude (see /topics/serdes-design-fundamentals). IEEE 802.3 therefore mandates Reed-Solomon FEC in the PCS. RS(528,514), called KR4 FEC, operates on 10-bit symbols and is the lighter variant common on 25G/100G NRZ backplane and cable links. RS(544,514), called KP4 FEC, is the stronger variant and the workhorse for PAM4 lanes (50G/100G per lane and the 400G/800G ports built from them); it adds more parity to handle the higher symbol-error rate of PAM4 and the burst errors that DFE error-propagation produces. The exact FEC is specified per PMD rather than strictly by signaling, but broadly KR4 pairs with NRZ and KP4 with PAM4. The interview point: FEC is not optional at these rates — it is a budgeted part of the link, and the BER spec is stated pre-FEC and post-FEC.
- How is PAM4 used in Ethernet, and how does it differ from NRZ links?
- PAM4 carries two bits per symbol using four amplitude levels, so a 100G electrical lane runs at ~53 Gbaud (Nyquist ~26.5 GHz) rather than the ~100 Gbaud (Nyquist ~50 GHz) an NRZ lane would need — halving the symbol rate and the channel bandwidth for the same bit rate, which is how Ethernet pushed per-lane rates from 25G NRZ to 50G and 100G without doubling channel loss. The cost is level separation: the three stacked eyes give roughly 9.5 dB less eye amplitude (the 20·log10(3) level-spacing penalty) than NRZ, so PAM4 links lean on stronger TX FFE / RX CTLE / DFE equalization and mandatory KP4 FEC. PAM4 also introduces gray coding (so a one-level error flips only one bit) and per-symbol metrics like SER alongside BER. Ethernet still uses NRZ at lower lane rates (10G, 25G) and on some backplane PMDs; the move to PAM4 is what defines the 50G-and-up generation. The underlying SerDes machinery is shared with PCIe (see /topics/pcie-gen5-gen6-explained).
- What does the PCS do beyond coding — what are alignment markers and lane distribution?
- Above 10G, Ethernet does not run on a single serial stream; the PCS scrambles the 64b/66b-encoded data and distributes it round-robin across a fixed number of PCS lanes (for example 20 PCS lanes for 100G), inserting periodic alignment markers into each lane. Those markers let the receiver identify each PCS lane, compensate for skew between physical lanes, and reassemble the stream in the correct order regardless of how the lanes were muxed by the PMA. This is what makes Ethernet medium-independent: the same PCS lanes can be carried over 4, 8, 10, or 20 physical lanes depending on the PMD, then realigned. For FEC-bearing PHYs, the RS-FEC sublayer adds its own alignment and transcoding. Candidates who can explain lane distribution, skew compensation, and alignment markers show they understand why Ethernet PHYs scale across so many media.
- How do auto-negotiation and link training work on copper Ethernet PHYs?
- On backplane (KR/KP) and copper-cable (CR) PMDs, two PHYs must agree on a common mode and then tune the channel before carrying traffic. Clause 73 auto-negotiation exchanges link-code words to select the highest common speed, FEC type (KR4 vs KP4), and Energy-Efficient Ethernet support. Then Clause 72-style link training (and its higher-rate equivalents) runs a closed loop: the receiver requests increment/decrement/preset adjustments to the remote transmitter FFE taps, measuring its own equalized eye, until the link converges. This is why backplane Ethernet can come up reliably across PCB and connector variation that an untrained link could not handle. Optical PMDs skip Clause 73 training but rely on their own DSP-based adaptive equalization. Knowing that copper links train their TX taps over the link — rather than being statically set — is a strong PHY-engineer signal and ties directly to signal integrity (see /topics/signal-integrity-fundamentals).
- How does Ethernet PHY differ from PCIe, and where does TSN sit relative to it?
- PCIe and Ethernet share the same SerDes fundamentals — PAM4, CDR, FFE/CTLE/DFE, FEC — but the protocol stacks differ. PCIe is a memory-mapped, point-to-point, credit-based load/store fabric with its own PHY logical layer and ordering rules (see /topics/pcie-gen5-gen6-explained), whereas Ethernet is a framed, packet-switched, addressable network defined by IEEE 802.3 with the PCS/PMA/PMD stack described here. Time-Sensitive Networking (see /topics/time-sensitive-networking-tsn) is a set of 802.1 standards that sit above the Ethernet MAC — scheduled traffic, time sync, and bounded latency — and depend on a correctly functioning PHY but do not change the PHY layer itself. Keeping these boundaries straight (PHY vs MAC vs the 802.1 control plane, and Ethernet vs PCIe) is exactly the kind of layering question interviewers use to separate depth from buzzwords.
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Essential AI-Native Skills for Ethernet PHY & High-Speed SerDes (PCS / FEC / 802.3)
Modern engineering work increasingly uses AI tools for design and code review, debugging, documentation, test and testbench generation, and workflow automation. The goal is not to let AI replace engineering judgment — it is to move faster while keeping verification discipline.
- Use AI to explain unfamiliar code, logs, waveforms, datasheets, or test failures.
- Break large problems into small, reviewable steps you can verify independently.
- Ask AI for hypotheses, then validate them against tests, measurements, simulations, or lab data.
- Version-control your analysis scripts, testbenches, and configs — keep changes small and reviewable.
- Document your assumptions, design tradeoffs, and debugging decisions.
- Verify AI output before trusting it: run the checks that fit the domain — unit tests, linters, simulations, or bench/lab measurements.
- Review AI output for correctness, edge cases, and real-world consequences.
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