Verilog Interview Questions (RTL Design) Interview Prep

Classic Verilog/RTL interview questions: the common trap and what a strong answer demonstrates

Frequently asked questions

Why does sequential logic use non-blocking assignments (<=) and combinational logic use blocking assignments (=)?

Non-blocking assignments (<=) schedule their right-hand sides to be evaluated, then all the left-hand sides update together at the end of the time step. That models hardware flip-flops correctly: every flop in an always @(posedge clk) block samples its input on the same clock edge, so order between statements should not matter. If you used blocking (=) in a clocked block, statement order would change behavior and you can accidentally chain flops into a single combinational path (or create a shift register you did not intend). The mirror rule is that purely combinational logic in an always @(*) block should use blocking (=) so each intermediate value is computed and reused immediately within the same evaluation, like wires settling. The interview-safe rule of thumb is: non-blocking (<=) in clocked/sequential always blocks, blocking (=) in combinational always blocks, and never mix the two styles in one block.

What is the difference between an inferred flip-flop and an accidental latch, and how do I avoid the latch?

A flip-flop is inferred when you assign a signal inside an edge-triggered block, e.g. always @(posedge clk) q <= d. A latch is inferred when a combinational block (always @(*)) does NOT assign a value to a signal on every possible path -- the synthesizer keeps the old value, which requires a level-sensitive latch. The classic cause is an if without an else, or a case that does not cover all inputs and has no default, where the output is therefore "remembered" on the missing branches. To avoid it: assign a default value to every output at the top of the combinational block, always include an else, always include a default in case statements, and treat synthesis latch-inference warnings as errors. In SystemVerilog, declaring the block always_comb makes the tool flag incomplete assignments for you, which is why interviewers like to see always_comb instead of always @(*).

What is clock domain crossing (CDC) and why does a single flip-flop not fix metastability?

A clock domain crossing happens when a signal generated in one clock domain is sampled by a register in another, asynchronous clock domain. Because the source can change arbitrarily close to the destination clock edge, it can violate the destination flop setup/hold window and drive the flop into a metastable state where its output hovers between 0 and 1 before resolving unpredictably. A single flip-flop cannot fix this -- it only moves the metastable event to its own output. The standard single-bit fix is a two-flop (sometimes three-flop) synchronizer: the first flop may go metastable, but it is given a full clock period to settle before the second flop samples it, making the probability of propagated metastability (the mean-time-between-failures) acceptably low. Crucially, a synchronizer is only valid for a single bit. Multi-bit buses cannot use parallel two-flop synchronizers because the bits can resolve on different cycles and produce a value that never existed; multi-bit crossings need a different scheme. Gray coding works only where exactly one bit changes per step, such as a counter or FIFO pointer; an arbitrary multi-bit data bus is not Gray-natured, so it needs a bundled-data handshake (hold the data stable while a synchronized valid signals it is safe to sample) or a dual-clock (asynchronous) FIFO instead.

How do I design a synchronous FIFO and correctly generate full and empty flags?

A synchronous FIFO is a dual-port memory plus a write pointer and a read pointer that share one clock. You write at wr_ptr on a write when not full, read at rd_ptr on a read when not empty, and increment the respective pointer each time. The subtlety interviewers probe is distinguishing full from empty, because both occur when the pointers are equal. The standard trick is to make each pointer one bit wider than the address it indexes: empty is when the pointers are exactly equal (same wrap bit and same address), and full is when the addresses are equal but the wrap (MSB) bits differ. An alternative is to keep a separate occupancy counter that increments on write, decrements on read, and defines full and empty directly -- simpler to reason about but an extra adder. Because a synchronous FIFO has one clock, full and empty come from directly comparing the read and write pointers in that single domain -- no synchronizers are involved -- and you should note the simultaneous read-and-write case, where both pointers advance in the same cycle so occupancy is unchanged. The read-domain / write-domain split and Gray-coded pointer synchronization belong to the asynchronous FIFO: when read and write live in different clock domains you cannot compare pointers directly, so you Gray-code each pointer, synchronize it into the other domain with a two-flop synchronizer, then compare -- and there empty is generated in the read domain and full in the write domain. A strong answer states the extra-MSB pointer scheme for the synchronous case and keeps the cross-domain machinery scoped to the asynchronous FIFO.

STRONG vs WEAK answer: "What happens if you use blocking assignment in a clocked always block?"

WEAK answer: "It still works, blocking and non-blocking are basically the same, the simulator just runs the lines in order." This is wrong and is an instant red flag -- it shows the candidate does not understand the simulation event model or how RTL maps to flip-flops. STRONG answer: "It can create a simulation-vs-synthesis mismatch and unintended logic. With blocking (=) in always @(posedge clk), the statements execute top to bottom within the same time step, so b = a; c = b; makes c take the NEW value of a in the same cycle -- that collapses what should be two pipeline flops into one, or builds a combinational chain instead of a register stage. With non-blocking (<=), a and b are sampled first and all flops update together, giving the two-cycle pipeline the RTL intended. Synthesis infers flops from the edge sensitivity either way, so the gate-level netlist may differ from what RTL simulation showed -- the dreaded sim/synth mismatch. That is why the rule is non-blocking in sequential blocks." The strong answer names the mechanism (scheduling/update phases), the consequence (collapsed pipeline + sim/synth mismatch), and the rule.

How should I practice for a Verilog / RTL interview?

Practice by writing and simulating small, classic RTL blocks until they are reflexive -- do not just read about them. A high-yield drill set: (1) code a parameterizable synchronous FIFO and prove your full/empty flags with a testbench that fills and drains it; (2) code a one-hot FSM (e.g. a traffic light or a simple bus arbiter) with clean next-state and output logic in separate always blocks, Moore first then Mealy; (3) code a two-flop clock-domain-crossing synchronizer for a single bit and explain why it would be wrong for a bus; (4) code a round-robin or fixed-priority arbiter; (5) code utility blocks interviewers love -- a rising/falling edge detector, a switch debouncer, a parameterized counter, and a Gray-code counter. For each one: lint it (catch latch inference, incomplete sensitivity lists, width mismatches), simulate it with a self-checking testbench, and be ready to draw the schematic it synthesizes to. Then practice explaining the design out loud in two minutes, because RTL interviews are as much about clear reasoning -- reset strategy, clocking, failure modes -- as about syntax. Use always_ff / always_comb in SystemVerilog so the tool enforces your intent.

What is the difference between synchronous and asynchronous reset, and how do interviewers expect you to reason about it?

A synchronous reset is sampled only on the active clock edge: always @(posedge clk) if (!rst_n) q <= 0; else q <= d. It keeps the reset inside the timing-analyzed clock path and, because it is only sampled at the active clock edge, it ignores reset pulses that fall between edges -- but it does not robustly filter glitches, since a glitch present at the sampling edge still takes effect; it also DOES need a running clock to take effect. An asynchronous reset takes effect immediately, independent of the clock: always @(posedge clk or negedge rst_n) if (!rst_n) q <= 0; else q <= d. It resets even with no clock, but its release (de-assertion) can violate the flop recovery/removal timing and cause metastability if it de-asserts near a clock edge. The widely-used compromise is asynchronous assertion, synchronous de-assertion -- a "reset synchronizer" that asserts reset immediately but releases it synchronized to the clock so all flops leave reset on the same edge. A strong answer names the recovery/removal timing risk and the reset-synchronizer pattern rather than just stating which keyword goes in the sensitivity list.

What is the difference between a Moore and a Mealy FSM, and one-hot versus binary state encoding?

A Moore machine output depends only on the current state, so it reacts one cycle later; that output is glitch-free only if it is registered, because a purely combinational decode of the state bits can still glitch as those bits settle. A Mealy machine output depends on the current state AND the current inputs, so it can react in the same cycle (fewer states, lower latency) but its outputs can glitch with the inputs and are harder to time. Interviewers like you to state the latency-versus-states tradeoff and to register Mealy outputs when you need clean timing. On encoding: binary encoding uses ceil(log2 N) flops for N states -- fewer flops, but more combinational decode logic. One-hot uses one flop per state with exactly one bit set -- more flops but trivial, fast next-state and output decode (just check one bit), which is why it is often preferred in FPGAs that are flop-rich. A strong answer also keeps next-state logic, state register, and output logic in clearly separated always blocks (combinational next-state in always_comb, the register in always_ff) and includes a safe default/recovery for illegal states.

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