Digital Logic Interview Prep
Digital logic interview prep for gates, Boolean algebra, combinational and sequential logic, FSMs, counters, setup and hold timing, and synchronous design.
Quick answer
Digital logic is the foundation layer of digital hardware: the discipline of building circuits from binary signals, logic gates, and storage elements that compute, store, and sequence data.
Digital logic is the substrate every hardware, RTL, FPGA, ASIC, and verification role builds on, so interviewers use it to test whether a candidate reasons from gates up to working, timing-correct hardware rather than reciting definitions.
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Wireless / RF / hardware engineering
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Wireless / RF / hardware engineering
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Key points
- Combinational logic computes outputs from current inputs only (Boolean, bounded by propagation delay); sequential logic adds clocked state via latches, flip-flops, and registers.
- The maximum clock frequency is set by the critical path: Tclk ≥ clock-to-Q + longest combinational delay + setup time.
- Setup/hold violations cause metastability; asynchronous or cross-clock-domain inputs need a synchronizer (two flip-flops), which lowers but never eliminates the failure probability (MTBF).
- Latch (level-sensitive) vs flip-flop (edge-triggered) is the most-tested distinction; an accidentally inferred latch is a classic RTL bug.
- FSMs must define reset and illegal-state recovery; know Mealy (outputs = state + input) vs Moore (outputs = state only).
What it is
Digital logic is the foundation layer of digital hardware: the discipline of building circuits from binary signals, logic gates, and storage elements that compute, store, and sequence data. It divides into two halves. Combinational logic — AND/OR/NOT/NAND/XOR gates plus multiplexers, decoders, and adders — computes outputs purely from the current inputs; its behavior is described by Boolean algebra and its cost is gate count and propagation delay. Sequential logic adds memory through latches, flip-flops, and registers, so outputs depend on both the current inputs and stored state, and a clock decides when that state advances. On top of these primitives sit finite-state machines, counters, and the datapath-plus-control structures that become processors, memory controllers, bus interfaces, and FPGA designs. The defining constraint of real digital design is not logical correctness alone but timing: in single-cycle synchronous design every register-to-register path must propagate and settle within a clock period (multicycle, false, and clock-domain-crossing paths are the explicit exceptions), and every flip-flop has setup and hold windows that must be respected or the circuit can go metastable. That is why practical digital logic is taught as synchronous design — a single clock, edge-triggered registers, and static timing analysis — rather than ad-hoc gate wiring.
Why interviewers ask
Digital logic is the substrate every hardware, RTL, FPGA, ASIC, and verification role builds on, so interviewers use it to test whether a candidate reasons from gates up to working, timing-correct hardware rather than reciting definitions. The combinational-versus-sequential distinction is the opening probe: a strong answer explains that combinational outputs follow inputs after a propagation delay while sequential outputs hold state across clock edges, and connects that to where glitches and hazards arise. Timing is the depth probe — setup time, hold time, and clock-to-Q, and how they bound the maximum clock frequency through Tclk ≥ Tclk-to-Q + Tcomb + Tsetup. Interviewers escalate to metastability: what happens when an asynchronous input violates a setup or hold window, why a two-flip-flop synchronizer reduces but never eliminates the failure probability, and how that ties to MTBF. Finite-state-machine questions check whether you define reset and illegal-state recovery and whether you can separate Mealy (outputs depend on state and input) from Moore (outputs depend on state only). Candidates who map a Boolean expression to gate count, critical-path delay, and area — instead of treating logic as pure math — signal readiness for real RTL and silicon work.
Common mistakes
The most common mistake is confusing latches and flip-flops: a latch is level-sensitive (transparent while its enable is asserted) and a flip-flop is edge-triggered (captures only on the clock edge). Accidentally inferring a latch in RTL — by not assigning a signal on every branch of a combinational block — is one of the most-flagged synthesis warnings because it breaks the clean register-to-register timing model. A second mistake is treating timing as an afterthought: writing logically-correct combinational paths too long to meet the clock period, or ignoring hold violations on short paths. A third is designing FSMs without reset and illegal-state recovery, so the machine can lock in an unreachable state after a glitch or at power-up. A fourth is sampling asynchronous or cross-clock-domain signals directly instead of through a synchronizer, which invites metastability that propagates unpredictably. A fifth is learning Boolean algebra as theory without connecting it to hardware — minimizing literals does not always minimize delay or area, and a balanced gate tree can beat a minimal-literal cascade on the critical path. Finally, candidates often blur Mealy and Moore machines, or treat unregistered combinational feedback as legitimate state when it actually causes oscillation or unintended latches.
Storage elements compared: latch vs D flip-flop vs register
| Element | Triggering | When it updates | Timing behavior | Typical use |
|---|---|---|---|---|
| Level-sensitive latch | Level (while enable asserted) | Transparent the whole time enable is high | Harder to analyze; can pass glitches; enables time-borrowing | Intentional time-borrowing or some low-power/custom cells — generally avoided in standard RTL |
| D flip-flop | Edge (rising or falling) | Captures D only at the active clock edge | Clean setup/hold window; static-timing friendly | The default state element in synchronous design |
| Register | Edge (shared clock) | A bank of D flip-flops updating together | Same as a flip-flop, applied to a multi-bit value | Holding multi-bit data: pipeline stages, datapath, control words |
Sample interview questions
- A synchronous register-to-register path has clock-to-Q = 0.3 ns, longest combinational delay = 2.0 ns, and setup time = 0.2 ns. Ignoring clock skew, what is the maximum clock frequency?
- A. 500 MHz, taken as 1 / 2.0 ns using only the combinational delay
- B. 400 MHz — the minimum period is Tclk-to-Q + Tcomb + Tsetup = 0.3 + 2.0 + 0.2 = 2.5 ns, so fmax = 1 / 2.5 ns = 400 MHz ✓
- C. 2 GHz, taken as 1 / (0.3 ns + 0.2 ns)
- D. Unbounded, because hold time rather than setup time limits clock speed
The maximum frequency is set by the longest register-to-register path: Tclk(min) = Tclk-to-Q + Tcomb(max) + Tsetup = 0.3 + 2.0 + 0.2 = 2.5 ns, so fmax = 400 MHz. Setup time is the long-path (maximum-frequency) constraint; hold time is a short-path constraint that must hold at any frequency and does not set fmax. Option A drops clock-to-Q and setup; the others misattribute the limiting terms.
- An asynchronous signal from another clock domain is sampled directly by a single flip-flop in your domain. What is the correct concern and fix?
- A. No concern — a flip-flop always resolves to a valid 0 or 1 within one cycle
- B. The flip-flop can go metastable if the edge violates setup/hold; add a two-flip-flop synchronizer so any metastable state settles before use, lowering (never eliminating) the failure probability ✓
- C. Replace the flip-flop with a level-sensitive latch, which cannot go metastable
- D. Add a combinational glitch filter — metastability is just a glitch
Sampling an input that violates the setup/hold window can drive a flip-flop metastable, with the output hovering between levels for an unbounded time. The standard fix is a synchronizer — typically two back-to-back flip-flops — giving any metastable state most of a clock period to resolve before downstream logic uses it. This reduces the failure probability (quantified by MTBF) but never reaches zero. Latches do not avoid metastability, filtering does not address it, and the "always resolves in one cycle" claim is the misconception under test.
- In an RTL combinational block describing next-state logic, you forget to assign an output on one branch of an if statement. What does synthesis most likely infer, and why is it flagged?
- A. A flip-flop, which is harmless
- B. A level-sensitive latch — the output must hold its previous value when no branch assigns it; inferred latches complicate static timing analysis and usually signal a coding bug ✓
- C. Nothing — the tool optimizes the missing branch away
- D. A combinational feedback loop that always oscillates
When a combinational block does not assign a signal on every path, the synthesized hardware must remember the previous value, which requires a level-sensitive latch. Inferred latches are flagged because they are usually unintended, they break the clean register-to-register timing model (latches are transparent), and they often indicate a bug. The fix is to assign every output on every branch, or set a default at the top of the block — one of the most common RTL lint warnings.
Frequently asked questions
- What is digital logic?
- Digital logic is the foundation of digital hardware. It uses binary signals, logic gates, Boolean algebra, flip-flops, and timing rules to build circuits that store, process, and control data. In practice, that means processors, memory controllers, interfaces, counters, finite-state machines, and FPGA designs.
- What is the difference between combinational and sequential logic?
- Combinational logic computes outputs from current inputs only. Sequential logic stores state, so outputs depend on the current inputs and the previous state. That distinction is the core of almost every digital logic interview.
- What is the difference between a latch and a flip-flop?
- A latch is level-sensitive: while enable is active, the output can follow the input. A flip-flop is edge-triggered: it captures input only on the active clock edge. In synchronous digital design, flip-flops are usually preferred because they make timing easier to control.
- What is setup time and hold time?
- Setup time is the minimum time data must be stable before the active clock edge. Hold time is the minimum time data must remain stable after the edge. If either window is violated, the flip-flop may capture the wrong value or become metastable.
- What is synchronous design?
- Synchronous design uses a clock to coordinate when state updates happen. That makes behavior more predictable because registers update at defined clock edges, which simplifies timing analysis, verification, and implementation.
- Why do interviewers ask digital logic questions?
- They want to know whether you can reason from basic gates to working hardware behavior. If you understand combinational logic, sequential logic, timing, and state machines, you can design and debug the digital systems that sit underneath RTL, FPGA, hardware, and validation work.
- How do setup time and hold time limit clock frequency?
- Setup time bounds the maximum clock frequency: the clock period must be at least clock-to-Q plus the longest combinational (critical-path) delay plus setup time, so Tclk ≥ Tclk-to-Q + Tcomb + Tsetup. Hold time is a different, short-path constraint — data must stay stable for a minimum time after the clock edge — and it must be satisfied at any frequency, so it does not set the maximum clock rate. Instead, hold violations force minimum path delays, sometimes fixed by adding buffers on the short path.
- What is metastability and how do you handle it?
- Metastability happens when a flip-flop samples an input that violates its setup or hold window — the output can hover between logic 0 and 1 for an unbounded time before resolving. You cannot prevent it for truly asynchronous or cross-clock-domain signals, so you contain it with a synchronizer: two back-to-back flip-flops that give any metastable state most of a clock period to settle before downstream logic uses the value. This lowers the probability of failure (quantified as mean time between failures, MTBF) but never drives it to zero.
- What is the difference between blocking and nonblocking assignments in RTL?
- In Verilog/SystemVerilog, blocking assignments (=) execute sequentially within a procedural block, like software statements, so a later line sees the updated value immediately. Nonblocking assignments (<=) sample all right-hand sides first and update the left-hand sides together at the end of the time step, modeling how real flip-flops all update on the same clock edge. The standard coding rule is: use nonblocking (<=) for sequential (clocked) logic and blocking (=) for combinational logic. Mixing them — especially using blocking assignments for clocked logic — causes simulation-versus-synthesis mismatches and race conditions, a classic source of RTL bugs.
Related topics
Essential AI-Native Skills for Digital Logic
Modern engineering work increasingly uses AI tools for design and code review, debugging, documentation, test and testbench generation, and workflow automation. The goal is not to let AI replace engineering judgment — it is to move faster while keeping verification discipline.
- Use AI to explain unfamiliar code, logs, waveforms, datasheets, or test failures.
- Break large problems into small, reviewable steps you can verify independently.
- Ask AI for hypotheses, then validate them against tests, measurements, simulations, or lab data.
- Version-control your analysis scripts, testbenches, and configs — keep changes small and reviewable.
- Document your assumptions, design tradeoffs, and debugging decisions.
- Verify AI output before trusting it: run the checks that fit the domain — unit tests, linters, simulations, or bench/lab measurements.
- Review AI output for correctness, edge cases, and real-world consequences.
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