Semiconductor Devices Interview Prep
Semiconductor devices interview prep — band theory, PN junctions, BJT and MOSFET physics, short-channel effects, and device-level limits on circuit performance.
Quick answer
Semiconductor Devices covers the physics underlying every modern electronic device.
Semiconductor-device questions appear in every analog IC, RF IC, power-electronics, photonics, and process-engineering interview, and they show up at hardware-systems interviews when device-level limits matter.
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CompoundLearn editorial team
Wireless / RF / hardware engineering
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CompoundLearn editorial team
Wireless / RF / hardware engineering
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What it is
Semiconductor Devices covers the physics underlying every modern electronic device. Standard topics include atomic and crystal structure of semiconductors, energy-band theory and the Fermi-Dirac distribution, intrinsic and extrinsic carriers, donor and acceptor doping, drift and diffusion currents (Einstein relation, mobility, conductivity), the continuity equation and minority-carrier transport, generation-recombination processes (Shockley-Read-Hall, Auger, radiative), the PN junction at equilibrium and under bias (depletion region, built-in potential, junction capacitance, Shockley diode equation, breakdown mechanisms), the BJT (Ebers-Moll, Gummel-Poon, current gain, Early effect, saturation), the MOSFET (threshold voltage, strong/weak/moderate inversion, square-law and short-channel models, body effect, subthreshold current, hot-carrier and breakdown effects), heterojunctions and HBTs/HEMTs for III-V devices, an introduction to optoelectronic devices (LEDs, photodiodes, laser diodes, solar cells), an introduction to power devices (IGBTs, power MOSFETs, GaN HEMTs, SiC FETs), and a survey of process technology (lithography, doping, deposition, etching) and how device geometry affects performance. For engineering candidates, semiconductor devices is the prerequisite layer beneath analog IC design, RF circuits, power electronics, photonics, and any role that touches the physical layer of integrated circuits.
Why interviewers ask
Semiconductor-device questions appear in every analog IC, RF IC, power-electronics, photonics, and process-engineering interview, and they show up at hardware-systems interviews when device-level limits matter. Strong interviewers probe whether candidates can reason from device physics to circuit behavior — derive transconductance from the square-law MOSFET model, explain why output resistance r_o degrades in short channels (channel-length modulation), or quantify why bipolar transistors have higher transconductance per bias current than MOSFETs (because of the exponential I-V vs the square-law). They probe junction capacitance and its effect on RF circuit Q, drain-induced barrier lowering and its impact on subthreshold leakage, and the body effect and its consequence for cascode-stack design. Photonics interviews probe direct-bandgap material selection, pn-junction biasing for LED operation, and the connection between bandgap and emission wavelength. Power-electronics interviews probe breakdown mechanisms (avalanche vs Zener), trade-offs between conductivity (low Ron) and breakdown voltage in vertical power devices, and the wide-bandgap revolution (GaN, SiC). The strongest candidates fluently switch between band-diagram pictures, equivalent-circuit pictures, and process-cross-section pictures, and they quote canonical numbers (n_i for silicon at room temperature, V_T thermal voltage, typical mobilities, typical breakdown fields). Senior interviews probe how device-physics limits cascade into system-level constraints — for example, why MOSFET subthreshold slope is bounded at 60 mV/decade by the Boltzmann distribution.
Common mistakes
The most common mistake is treating the diode and transistor equations as black-box formulas without knowing where the assumptions come from — candidates apply the Shockley equation in regions where it breaks (high injection, series resistance, depletion-region recombination) and report wrong currents. A second mistake is on the MOSFET square-law: candidates use it in deep short-channel devices where velocity saturation has changed the I-V from quadratic toward linear, overestimating transconductance significantly. A third mistake is on body effect: candidates ignore it in cascode stacks where the source of an upper transistor is at non-zero voltage, missing that V_T shifts and the small-signal model needs the body term g_mb. A fourth mistake on the BJT is to apply DC current gain β at AC frequencies without accounting for f_T and the high-frequency degradation — at frequencies above f_T, β drops below 1 and the device cannot amplify. A fifth mistake on subthreshold operation is to assume the MOSFET is "off" — modern low-power design exploits subthreshold conduction (where I_D depends exponentially on V_GS), and ignoring it underestimates leakage by orders of magnitude. A sixth mistake on PN junctions is to confuse forward-bias diffusion current (exponential in V) with reverse-bias drift saturation (constant I_S, plus generation in the depletion region) — the two are different physical mechanisms with different temperature dependence. A seventh mistake on capacitance is to confuse junction capacitance (depletion-region width, C_j) with diffusion capacitance (minority-carrier storage, dominant in forward bias), and apply junction-capacitance formulas in regimes where diffusion capacitance is bigger by orders of magnitude. An eighth mistake on temperature is to forget that almost everything in semiconductor physics is exponential in temperature: I_S, leakage current, mobility, V_T — and these dependencies matter for any precision or wide-temperature design. Finally, candidates often miss that the Boltzmann limit on subthreshold slope (60 mV/decade at room temperature) is fundamental — only tunneling-based devices (TFETs) can break it, which is why power scaling has slowed in the FinFET era.
Frequently asked questions
- What is the difference between drift and diffusion currents in semiconductors?
- Drift current is the carrier flow driven by an applied electric field: J_drift = q·n·µ·E, where µ is mobility. Diffusion current is the flow from concentration gradients: J_diff = q·D·∇n, where D is the diffusion coefficient (Einstein relation: D/µ = kT/q). At equilibrium (zero bias) the two currents exactly cancel, giving no net current; under forward bias the barrier drops and diffusion current dominates (the net forward current), while in a reverse-biased junction drift dominates the small saturation current. Bipolar transistor base transport is diffusion-driven in a uniformly-doped base (minority-carrier diffusion across the neutral base — a graded base or HBT adds a built-in drift field), while MOSFET channel current is drift-driven (majority carriers in an inverted channel).
- How does the Shockley diode equation work, and where do the assumptions break?
- I = I_S · (exp(qV/(n·kT)) - 1), where I_S is reverse saturation current and n is the ideality factor (1 for ideal diodes, closer to 2 with recombination-dominated current). At room temperature, kT/q ≈ 26 mV, so for an ideal diode (n≈1) each 60 mV increase in V multiplies current by 10 — n·60 mV per decade in general. The equation breaks down at high forward bias (series resistance dominates), at high reverse bias (avalanche or Zener breakdown), and at very low currents (recombination/generation in the depletion region). Real diodes also have temperature dependence — V_F drops about -2 mV/°C at constant current.
- What determines threshold voltage in a MOSFET?
- V_T depends on flatband voltage (work-function difference between gate and substrate, plus oxide-charge effects), the body doping concentration (sets surface potential at strong inversion), the oxide capacitance C_ox, and substrate body bias V_BS. Higher doping raises V_T; thinner oxide lowers it; positive substrate bias (for NMOS) raises it via body effect γ·(√(2φ_F + V_BS) - √(2φ_F)). Modern processes engineer V_T per device class: low-V_T for high-speed paths, high-V_T for low-leakage paths, with multi-V_T design enabling power-vs-performance tradeoffs.
- What is short-channel effect and why does it matter?
- In short-channel MOSFETs, the drain-induced electric field penetrates significantly into the channel near the source, lowering the barrier and increasing subthreshold leakage (DIBL — drain-induced barrier lowering). Velocity saturation also kicks in: at high lateral fields, carrier velocity saturates instead of continuing to grow with E, which softens the saturation-region I-V curve from quadratic (long channel) toward linear (deep short channel). Short-channel effects motivate halo doping, lightly-doped drain (LDD) extensions, and the move from planar bulk to FinFET and gate-all-around architectures.
- How does a PN junction form a depletion region, and what determines its width?
- At the metallurgical junction, electrons from N-side diffuse into P-side, holes from P diffuse into N. The diffused carriers recombine and leave behind ionized dopants (positive on N-side, negative on P-side), forming a depletion region with no mobile carriers. The internal electric field from the ionized donors and acceptors opposes further diffusion until equilibrium is reached. Width follows from Poisson's equation: W = √(2·ε·V_bi·(N_A + N_D)/(q·N_A·N_D)). Higher doping shrinks the depletion region; reverse bias widens it; that width controls the small-signal capacitance C_j of the junction, important in RF and high-speed switching.
- What is the difference between direct and indirect bandgap, and why does it matter?
- Direct bandgap (GaAs, InGaAs, GaN, InP): conduction-band minimum and valence-band maximum align at the same crystal momentum, so electron-hole recombination emits a photon directly — useful for LEDs, laser diodes, photodetectors. Indirect bandgap (Si, Ge): the minima are at different k-vectors, so radiative recombination requires a phonon to conserve momentum — much less efficient, which is why silicon is poor at light emission. For photovoltaics and photodetection, indirect bandgap absorbs light less efficiently per unit thickness, but silicon's manufacturing cost dominates everything else for terrestrial PV.
Related topics
Essential AI-Native Skills for Semiconductor Devices
Modern engineering work increasingly uses AI tools for design and code review, debugging, documentation, test and testbench generation, and workflow automation. The goal is not to let AI replace engineering judgment — it is to move faster while keeping verification discipline.
- Use AI to explain unfamiliar code, logs, waveforms, datasheets, or test failures.
- Break large problems into small, reviewable steps you can verify independently.
- Ask AI for hypotheses, then validate them against tests, measurements, simulations, or lab data.
- Version-control your analysis scripts, testbenches, and configs — keep changes small and reviewable.
- Document your assumptions, design tradeoffs, and debugging decisions.
- Verify AI output before trusting it: run the checks that fit the domain — unit tests, linters, simulations, or bench/lab measurements.
- Review AI output for correctness, edge cases, and real-world consequences.
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