What is the difference between BJT and MOSFET, and when do you choose each?

BJT: current-controlled (base current sets collector current via β), exponential I-V (Shockley equation), high transconductance per unit current, but consumes static base current. MOSFET: voltage-controlled (V_GS sets drain current), square-law in saturation (long channel) or near-linear in short-channel devices, infinite DC input impedance. MOSFETs dominate digital and modern analog because of zero static gate current and excellent switching; BJTs persist in low-noise amplifiers, voltage references, and RF where transconductance/bias-current ratio matters.

How do you design an op-amp inverting amplifier, and what limits its bandwidth?

For an ideal op-amp with feedback resistor Rf and input resistor Rin, gain = -Rf/Rin and input impedance = Rin (because the inverting node is a virtual ground). Bandwidth is gain-bandwidth-product (GBW) divided by the closed-loop gain magnitude — a 1 MHz GBW op-amp at gain 100 has 10 kHz of useful bandwidth. Slew-rate limits large-signal bandwidth separately: a sinewave of amplitude V and frequency f requires slew rate ≥ 2π·f·V or it will distort. Real-world limits also include input bias current, offset voltage, and noise.

What is small-signal analysis and why is it useful?

Small-signal analysis linearizes a non-linear device (BJT, MOSFET, diode) around its DC operating point by replacing it with a linear equivalent (g_m current source, r_pi base resistance, r_o output resistance). The linearized circuit then yields to standard linear-circuit analysis, giving voltage gain, input/output impedance, and bandwidth — all valid for signal amplitudes much smaller than the bias quantities. Small-signal is exactly Taylor expansion to first order around the DC operating point, and it fails for large signals where higher-order terms produce harmonic distortion.

How does an op-amp Bode plot tell you about stability?

A negative-feedback amplifier is unstable when the loop gain magnitude is ≥ 1 at the frequency where loop phase reaches -180°. The phase margin (extra phase at the unity-gain frequency above -180°) and gain margin (how much loop gain falls below 1 when phase is at -180°) measure stability robustness. Internally compensated op-amps add a dominant pole that gives the open-loop response a -20 dB/decade slope at unity-gain crossover, giving a large phase margin in voltage-follower (gain = 1) configuration — approaching 90° only for an ideal single-pole loop, and typically ~45-70° in real op-amps once secondary poles are included — and degrading further as the closed-loop gain decreases or as additional poles enter the loop.

What is the role of bypass and decoupling capacitors?

Bypass capacitors keep the supply rail at AC ground close to the chip — when the chip's current draw spikes (digital edges, amplifier large-signal), the local capacitor sources the transient charge instead of forcing it through PCB-trace inductance, which would induce supply ringing and ground bounce. Decoupling caps come in tiered values (10 µF for low frequencies, 100 nF for mid, 1 nF or smaller for high) because each cap has self-resonance — bigger caps have lower SRF and stop bypassing above their resonance. Modern PCBs cluster decoupling caps within mm of the chip's power pins.

How do you bias a common-emitter amplifier, and why does emitter degeneration help?

Common-emitter biasing uses a voltage divider on the base plus a stable emitter resistor R_E. The DC base voltage sets the emitter voltage, which sets the emitter (and approximately collector) current. R_E provides negative feedback for DC: if temperature shifts move the BJT operating point, the emitter voltage shifts to compensate, stabilizing I_C. Small-signal gain becomes -R_C / (R_E + r_e), where r_e ~ V_T/I_C. Emitter degeneration trades voltage gain for linearity, predictability, and bandwidth — the gain is set by external resistors instead of variable transistor parameters.

Electronics Interview Prep

Electronics interview prep — diodes, BJT and MOSFET amplifiers, biasing, op-amps, frequency response, feedback, and stability for analog EE candidates.

Quick answer

Electronics covers the analysis and design of circuits using non-linear active devices — primarily diodes, BJTs, and MOSFETs — operating in linear (small-signal) regimes.

Electronics questions are the core of every analog and mixed-signal interview, and a screening filter at hardware-systems and RF interviews.

Editorial review

Written by

CompoundLearn editorial team

Wireless / RF / hardware engineering

Reviewed by

CompoundLearn editorial team

Wireless / RF / hardware engineering

Last reviewed

June 21, 2026

Built from curated topic maps, editorial validation, and subject-matter review so the page stays aligned with the interview intent and the current content pipeline.

Key points

BJT is current-controlled with exponential I_C(V_BE) and a finite base current; MOSFET is voltage-controlled with (near) square-law I_D(V_GS) and zero DC gate current — pick the device by transconductance-per-current, noise, and switching needs.
A single-stage gain has to be biased into the active/saturation region first; small-signal models (hybrid-π, g_m, r_o) are only a first-order linearization around that DC operating point.
Closed-loop bandwidth ≈ GBW / closed-loop gain (a small-signal limit); slew rate sets a separate large-signal limit — an undistorted sinewave of amplitude V at frequency f needs SR ≥ 2·π·f·V.
The Miller effect multiplies a common-emitter/source feedback capacitance by (1 + |Av|), creating the dominant high-frequency input pole; a cascode pins the input device at unity local gain to kill it.
Stability is a loop-gain (T = A·β) question, not a closed-loop-gain question: you need positive phase margin where |T| = 1 — and load capacitance, layout parasitics, and supply impedance can erode the margin the textbook Bode plot shows.

What it is

Electronics covers the analysis and design of circuits using non-linear active devices — primarily diodes, BJTs, and MOSFETs — operating in linear (small-signal) regimes. Standard topics include diode physics and the Shockley equation, rectifier and clamping circuits, BJT physics (Ebers-Moll, Gummel-Poon), MOSFET physics (long-channel and short-channel models), DC biasing for stable operating points (voltage divider, current mirror), small-signal models (h-parameters, hybrid-π for BJT; g_m and r_o for MOSFET), single-stage amplifiers (common-emitter/source, common-base/gate, common-collector/drain), differential pairs and current mirrors as building blocks, multistage amplifiers and cascading effects, frequency response (low-frequency and high-frequency rolloff, Miller effect), feedback theory (negative feedback for gain stability and bandwidth extension, positive feedback for oscillators), op-amp circuits (inverting, non-inverting, summing, integrator, differentiator, instrumentation amplifier), op-amp non-idealities (offset, drift, noise, bandwidth, slew rate), basic oscillators and waveform generation, and an introduction to switching power converters. For engineering candidates, electronics is the prerequisite layer beneath analog IC design, RF circuits, sensor interfaces, and any mixed-signal system. The same building blocks (current mirror, differential pair, output stage) recur in every analog IC, and fluency with biasing, gain, and stability analysis is the screening filter for analog and mixed-signal interviews.

Why interviewers ask

Electronics questions are the core of every analog and mixed-signal interview, and a screening filter at hardware-systems and RF interviews. Strong interviewers ask whiteboard amplifier design — pick a BJT or MOSFET, bias it, set the gain, derive the bandwidth, and discuss stability — to surface whether the candidate has actually built circuits or just memorized formulas. They probe small-signal fluency by asking for the input impedance and gain of a common-emitter or common-source stage by inspection, then add complications: emitter degeneration, source follower, cascode. They probe op-amp depth: derive the closed-loop gain of a non-inverting amplifier, explain Miller compensation, sketch the Bode plot of a feedback loop and find the phase margin. The strongest candidates fluently switch between BJT and MOSFET pictures, between time-domain large-signal behavior (slew-rate limited transients) and frequency-domain small-signal pictures (Bode plots), and between idealized analysis and real-world constraints (offset, noise, parasitic capacitance, layout). Senior interviews additionally probe non-linearities (harmonic distortion, intermodulation), noise (input-referred noise calculations, noise figure), and packaging effects (bond-wire inductance, substrate coupling) — areas that separate analog generalists from designers who have actually shipped silicon.

Common mistakes

The most common mistake is mishandling DC biasing — candidates set up the small-signal analysis correctly but pick an operating point in cutoff or saturation, where the small-signal model does not apply. A second mistake is using a saturated or cutoff transistor for amplification — the device must be in active (BJT) or saturation (MOSFET) region for linear amplification. A third mistake is ignoring the Miller effect at high frequency — the feedback capacitance (C_bc / C_gd) of a common-emitter or common-source stage appears at the input multiplied by (1 + |voltage gain|), which dramatically lowers the input pole and is the dominant high-frequency limit in many designs. A fourth mistake is conflating loop gain and closed-loop gain — stability is determined by loop gain (T = A·β), while gain accuracy and bandwidth are determined by closed-loop gain (1/β when T >> 1); candidates analyze stability with the wrong quantity and reach wrong conclusions. A fifth mistake is on op-amp limits: candidates apply ideal-op-amp results everywhere and ignore that real op-amps have finite GBW (closed-loop bandwidth = GBW / gain), finite slew rate (limits large-signal bandwidth), input bias current (causes offset across mismatched source impedances), and input offset voltage (multiplied by closed-loop gain at the output). A sixth mistake is on stability: candidates compute phase margin from the open-loop Bode plot but forget that adding load capacitance, layout parasitics, or supply impedance can shift poles and erode margin in ways the textbook plot does not show. A seventh mistake is sloppy use of small-signal parameters — using h-parameters from a different operating point, or treating g_m as constant when it scales with bias current. An eighth mistake is on biasing stability: candidates use a fixed-base-voltage scheme (no emitter resistor) and report "stable" gain, missing that temperature variation in V_BE can shift the operating point arbitrarily — emitter degeneration or active biasing (current mirror) is required for production designs. Finally, candidates often ignore noise: an amplifier's output noise is set by the input-referred noise of the first stage and the source impedance, and chasing more gain in later stages does not help.

BJT vs MOSFET as an amplifying device: what the choice actually trades

Property	BJT	MOSFET
Control variable	Base current sets I_C (current-controlled)	Gate–source voltage sets I_D (voltage-controlled)
Transfer law	Exponential: I_C ≈ I_S·exp(V_BE / V_T)	Square-law in saturation (long channel); near-linear when velocity-saturated (short channel)
Transconductance	g_m = I_C / V_T — highest g_m for a given bias current	g_m = √(2·μ·Cox·(W/L)·I_D) — lower g_m per microamp, set by W/L
DC input current	Finite base current (I_C / β) — loads the source	Essentially zero gate current at DC — infinite DC input resistance
As a switch	V_CE(sat) ≈ 0.1–0.3 V drop; stores charge, slower turn-off	Resistive R_DS(on); no minority-carrier storage, clean fast switching
Where it wins	Low-noise / low-V_offset front ends, bandgap references, some RF where g_m/I_C matters	Digital, switching, and most modern analog/mixed-signal integration

Sample interview questions

An op-amp has a gain–bandwidth product of 10 MHz and a slew rate of 1 V/µs. You configure it for a closed-loop gain of 10. Which limit do you hit first for a 5 V peak (10 V peak-to-peak) output sinewave, and at roughly what frequency?
- A. Small-signal bandwidth at 1 MHz — slew rate never matters below the closed-loop bandwidth
- B. Closed-loop bandwidth is GBW/gain = 1 MHz, but the 5 V-peak signal is slew-limited to SR / (2·π·V) ≈ 32 kHz, so slew rate bites first ✓
- C. Slew rate sets 10 MHz and bandwidth sets 100 kHz, so bandwidth bites first
- D. Neither limit applies because both are specified at unity gain only
Two independent limits. The small-signal closed-loop bandwidth is GBW / closed-loop gain = 10 MHz / 10 = 1 MHz. The large-signal limit is slew rate: an undistorted sinewave needs SR ≥ 2·π·f·V, so f_max ≈ SR / (2·π·V) = 1 V/µs / (2·π·5 V) ≈ 32 kHz. Because 32 kHz is far below the 1 MHz small-signal bandwidth, the output goes into slew-rate (triangular-wave) distortion long before the gain rolls off. The trap in option A is assuming bandwidth always dominates; slew rate is amplitude-dependent and frequently the real ceiling for large outputs.
A common-emitter stage with voltage gain −40 uses a transistor with base–collector capacitance C_µ = 2 pF. Why does its high-frequency response suffer, and how does a cascode fix it without losing gain?
- A. C_µ is too small to matter; the limit is purely the load resistor
- B. The Miller effect makes C_µ look like (1 + |Av|)·C_µ ≈ 82 pF at the input, forming a low input pole; a cascode holds the input device at unity local gain so C_µ is no longer multiplied ✓
- C. C_µ shorts the output at high frequency; adding a cascode increases it deliberately
- D. The cascode raises the gain to compensate, so bandwidth is irrelevant
The Miller effect reflects the feedback capacitance C_µ to the input multiplied by (1 + |Av|): here (1 + 40)·2 pF ≈ 82 pF. Driven by the source/base resistance, that large effective input capacitance forms the dominant high-frequency pole and collapses bandwidth. A cascode stacks a common-base/gate device above the input transistor so the input device sees a low (≈ unity) local voltage gain at its collector/drain. With Av_local ≈ 1, C_µ is barely multiplied, the input pole moves up, and the overall gain is recovered by the high output impedance of the upper device — high gain and wide bandwidth at the cost of one extra transistor and some output voltage headroom.
A candidate biases a BJT common-emitter stage with a fixed base voltage and no emitter resistor, then reports the gain as "stable." What is wrong, and what is the standard fix?
- A. Nothing — fixing the base voltage fixes the collector current directly
- B. V_BE drifts ≈ −2 mV/°C, so a fixed base voltage lets I_C run away with temperature; add an emitter resistor (degeneration) or active current-source biasing to stabilize the operating point ✓
- C. The gain is unstable because the AC signal changes V_BE; add a larger input capacitor
- D. Fixed-base bias is correct; the only fix needed is a bypass capacitor on the collector
Fixing V_BE does not fix I_C, because I_C depends exponentially on V_BE and V_BE itself drifts about −2 mV/°C. A fixed base voltage therefore lets the operating point — and the small-signal gain that rides on it — wander with temperature and device spread, often into saturation. The production fix is negative DC feedback: an emitter resistor R_E so that any rise in I_C raises the emitter voltage and self-limits the base–emitter drive, or an active current mirror that sets I_C directly. Degeneration also makes the gain (≈ −R_C / (R_E + r_e)) depend on resistor ratios rather than on the temperature-sensitive r_e, trading raw gain for predictability.

Frequently asked questions

What is the difference between BJT and MOSFET, and when do you choose each?: BJT: current-controlled (base current sets collector current via β), exponential I-V (Shockley equation), high transconductance per unit current, but consumes static base current. MOSFET: voltage-controlled (V_GS sets drain current), square-law in saturation (long channel) or near-linear in short-channel devices, infinite DC input impedance. MOSFETs dominate digital and modern analog because of zero static gate current and excellent switching; BJTs persist in low-noise amplifiers, voltage references, and RF where transconductance/bias-current ratio matters.
How do you design an op-amp inverting amplifier, and what limits its bandwidth?: For an ideal op-amp with feedback resistor Rf and input resistor Rin, gain = -Rf/Rin and input impedance = Rin (because the inverting node is a virtual ground). Bandwidth is gain-bandwidth-product (GBW) divided by the closed-loop gain magnitude — a 1 MHz GBW op-amp at gain 100 has 10 kHz of useful bandwidth. Slew-rate limits large-signal bandwidth separately: a sinewave of amplitude V and frequency f requires slew rate ≥ 2π·f·V or it will distort. Real-world limits also include input bias current, offset voltage, and noise.
What is small-signal analysis and why is it useful?: Small-signal analysis linearizes a non-linear device (BJT, MOSFET, diode) around its DC operating point by replacing it with a linear equivalent (g_m current source, r_pi base resistance, r_o output resistance). The linearized circuit then yields to standard linear-circuit analysis, giving voltage gain, input/output impedance, and bandwidth — all valid for signal amplitudes much smaller than the bias quantities. Small-signal is exactly Taylor expansion to first order around the DC operating point, and it fails for large signals where higher-order terms produce harmonic distortion.
How does an op-amp Bode plot tell you about stability?: A negative-feedback amplifier is unstable when the loop gain magnitude is ≥ 1 at the frequency where loop phase reaches -180°. The phase margin (extra phase at the unity-gain frequency above -180°) and gain margin (how much loop gain falls below 1 when phase is at -180°) measure stability robustness. Internally compensated op-amps add a dominant pole that gives the open-loop response a -20 dB/decade slope at unity-gain crossover, giving a large phase margin in voltage-follower (gain = 1) configuration — approaching 90° only for an ideal single-pole loop, and typically ~45-70° in real op-amps once secondary poles are included — and degrading further as the closed-loop gain decreases or as additional poles enter the loop.
What is the role of bypass and decoupling capacitors?: Bypass capacitors keep the supply rail at AC ground close to the chip — when the chip's current draw spikes (digital edges, amplifier large-signal), the local capacitor sources the transient charge instead of forcing it through PCB-trace inductance, which would induce supply ringing and ground bounce. Decoupling caps come in tiered values (10 µF for low frequencies, 100 nF for mid, 1 nF or smaller for high) because each cap has self-resonance — bigger caps have lower SRF and stop bypassing above their resonance. Modern PCBs cluster decoupling caps within mm of the chip's power pins.
How do you bias a common-emitter amplifier, and why does emitter degeneration help?: Common-emitter biasing uses a voltage divider on the base plus a stable emitter resistor R_E. The DC base voltage sets the emitter voltage, which sets the emitter (and approximately collector) current. R_E provides negative feedback for DC: if temperature shifts move the BJT operating point, the emitter voltage shifts to compensate, stabilizing I_C. Small-signal gain becomes -R_C / (R_E + r_e), where r_e ~ V_T/I_C. Emitter degeneration trades voltage gain for linearity, predictability, and bandwidth — the gain is set by external resistors instead of variable transistor parameters.

Essential AI-Native Skills for Electronics

Modern engineering work increasingly uses AI tools for design and code review, debugging, documentation, test and testbench generation, and workflow automation. The goal is not to let AI replace engineering judgment — it is to move faster while keeping verification discipline.

Use AI to explain unfamiliar code, logs, waveforms, datasheets, or test failures.
Break large problems into small, reviewable steps you can verify independently.
Ask AI for hypotheses, then validate them against tests, measurements, simulations, or lab data.
Version-control your analysis scripts, testbenches, and configs — keep changes small and reviewable.
Document your assumptions, design tradeoffs, and debugging decisions.
Verify AI output before trusting it: run the checks that fit the domain — unit tests, linters, simulations, or bench/lab measurements.
Review AI output for correctness, edge cases, and real-world consequences.

Electronics — coming to the question bank

The adaptive practice engine is already live for core wireless, RF, and ML systems. Electronics isn't covered in the question bank yet — get notified when it's added.