Physical Design & PnR Interview Guide (Timing Closure) Interview Prep

ASIC backend (PnR) stages: what each does, its key concern, and a typical signoff check

Frequently asked questions

What are the main stages of the ASIC physical design (PnR) flow?

The classic place-and-route flow runs in order: floorplanning (die and core area, macro placement, IO ring, pin placement), power planning (the power grid / PDN and rails), placement of standard cells, clock tree synthesis (CTS) to distribute the clock, routing (global then detailed), and finally signoff. Signoff itself is several checks: static timing analysis (STA) across corners and modes, physical verification (DRC, LVS, antenna), and power-integrity analysis (IR drop and electromigration). Each stage feeds the next, and timing closure is iterative — you loop back when STA, congestion, or IR-drop checks fail.

What is the difference between a setup violation and a hold violation, and how is each fixed?

A setup violation means data arrives too late relative to the capturing clock edge — the data path is too slow for the clock period. You fix it by speeding up the data path (upsizing cells, using faster/low-Vt cells, restructuring logic) or, at the system level, by relaxing the clock (lower frequency) or applying useful skew to give that path more time. A hold violation means new data races through the path too fast and corrupts the value being latched at that same capturing edge — the path is too short relative to the clock. You fix it by adding delay (inserting buffers/delay cells) on the short path. The key interview point: setup is frequency-dependent and can often be traded against clock period, while hold is clock-relative and largely period-independent, which is why hold problems can survive to silicon if not closed.

What does clock tree synthesis (CTS) do and why does skew matter?

CTS builds the physical network that delivers the clock to every sequential element, inserting and sizing clock buffers/inverters to balance the tree. Its goals are to control clock skew (the difference in arrival time between sink pins) and insertion delay (latency from the clock source to the sinks) while meeting transition and power targets. The sign of skew matters, not just its magnitude. Using the convention skew = capture-clock arrival minus launch-clock arrival, positive capture skew helps setup (it borrows time for the setup path) but hurts hold, while negative capture skew hurts setup but helps hold; useful skew exploits exactly this, so modern CTS/CCOpt does not simply minimize skew — it shapes it. Because skew shifts the setup and hold timing windows in opposite directions depending on its sign, uncontrolled skew can create either setup or hold violations, not just one or the other. Clock-gating cells are usually inserted earlier by synthesis or low-power optimization; CTS builds the tree through and balances them, and may clone or optimize them.

Is routing the whole backend flow?

No. Routing is one stage, not the whole backend. Routing connects the placed cells using global routing (planning the rough paths and layer usage) followed by detailed routing (assigning exact tracks and vias, DRC-clean). But routing only happens after floorplanning, power planning, placement, and CTS, and it is followed by signoff — STA, physical verification, and power integrity. A candidate who equates backend with routing misses floorplanning quality, the power grid, clock tree balance, and the signoff loop that actually determines whether a chip works.

What is signoff in physical design?

Signoff is the final set of golden checks that say the layout is manufacturable and meets timing and power. It includes static timing analysis across multiple corners and modes (MCMM) with on-chip variation (OCV/AOCV) margins, physical verification — DRC (design-rule check), LVS (layout-versus-schematic) and antenna checks, and power integrity — IR-drop analysis on the PDN plus electromigration (EM) checks. Parasitic extraction (RC) of the routed design feeds the signoff STA. Tools like Synopsys PrimeTime are common for signoff STA, while StarRC or QRC handle extraction; the point is that signoff uses sign-off-grade engines and margins, not the faster in-tool estimates used during implementation.

Why is multi-corner multi-mode (MCMM) timing analysis important?

A chip must work across process, voltage, and temperature (PVT) variation and across different functional modes (e.g., functional vs test, high-power vs low-power). MCMM analyzes timing simultaneously across these corners and modes so that closing one corner does not break another. Treating STA as a single corner is a classic mistake: a path that meets setup at the slow corner may fail hold at the fast corner, since hold is typically worst at the fast (low-delay) corner and setup worst at the slow corner. On-chip variation modeling (OCV/AOCV) adds derating so the analysis stays pessimistic enough to be safe.

How do congestion and timing trade off during placement and routing?

Placement and routing constantly trade routability against timing. Packing timing-critical cells close together shortens nets and helps timing, but it can create routing congestion — too many nets competing for tracks in a region — which forces detours that hurt timing and can cause DRC violations. Placement-driven optimization spreads cells to relieve congestion while watching timing, and engineers manage it with cell spreading, blockages, layer assignment, and net weighting. The interview signal is recognizing that the best timing solution is useless if it cannot be routed DRC-clean.

What is an ECO flow in physical design?

An ECO (engineering change order) is a targeted, late-stage change applied without re-running the whole flow. Functional ECOs implement a logic fix; timing/signoff ECOs fix residual setup or hold violations found in signoff STA by inserting, resizing, or swapping a handful of cells and incrementally re-routing. ECOs are how teams close the last violations and respin metal layers (metal-only ECO) without disturbing the rest of a converged, verified design.

What does a strong versus weak physical design answer sound like?

A weak answer thinks routing is the whole backend, or gives the wrong setup versus hold fix (speeding up a path for hold, adding buffers for setup). A strong answer sounds like the candidate has run the loop: it reasons about the congestion versus timing tradeoff, fixes setup versus hold correctly (and knows that hold can survive to silicon because it is clock-relative rather than frequency-dependent), and treats signoff as multi-corner multi-mode rather than a single corner. The difference is systems-level fluency about how the stages interact, not just a list of stage names.

How should I prepare for a physical design / PnR / timing-closure interview?

Drill the loop directly. Practice reading a timing report and computing slack (arrival time versus required time), deciding a setup versus hold fix for a given violation, reasoning about a congestion hotspot and how to relieve it, and sequencing a timing-closure ECO that closes a residual violation. Be ready to explain why hold can fail at the fast corner while setup fails at the slow corner. For deep static timing analysis, study the static-timing-analysis-sta companion page.

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