Analog, Mixed-Signal & RFIC Design Interview Questions Interview Prep
What analog, mixed-signal, and RFIC design interviews test: transistor-level design, ADC/DAC, PLL, noise, layout parasitics, RFIC blocks, and mixed-signal verification.
Quick answer
Analog and mixed-signal design interviews test whether a candidate can reason about circuits at the transistor level under the non-idealities that dominate real silicon: finite gain, parasitics, noise, mismatch, and process-voltage-temperature spread.
Feedback stability and small-signal analysis are the most common analog interview deep-dive because nearly every useful analog block — op-amps, regulators, PLLs — is a closed loop, and a designer who cannot reason about poles, zeros, and phase margin will build circuits that ring or oscillate in silicon.
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Key points
- Start with small-signal analysis: dominant pole, gain-bandwidth, and feedback stability and phase margin.
- Master noise next: thermal, flicker (1/f), and sampled kT/C, and how they map to noise figure.
- Then mismatch and layout parasitics: common-centroid matching, Pelgrom scaling, and routing/parasitic effects.
- Build up to data converters and PLLs: ADC/DAC metrics, ENOB, and loop-bandwidth trade-offs.
- Finish with RFIC blocks and mixed-signal verification: LNA/mixer/PA, real-number modeling, and AMS co-simulation.
What it is
Analog and mixed-signal design interviews test whether a candidate can reason about circuits at the transistor level under the non-idealities that dominate real silicon: finite gain, parasitics, noise, mismatch, and process-voltage-temperature spread. The role designs the analog and RF building blocks that sit between the physical world and the digital core — operational amplifiers (see /topics/electronics), bandgap voltage references, low-dropout regulators (LDOs), phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs), data converters (ADCs and DACs), SerDes front-ends, and RF transceiver elements such as low-noise amplifiers, mixers, and power-amplifier drivers. Mixed-signal means analog and digital share one die, so the designer must also handle the interfaces between them: level shifting across power domains, clock-domain crossings into a converter, and isolating sensitive analog nodes from digital switching noise injected through the shared substrate and supplies. The day-to-day workflow spans three connected disciplines. Circuit design and hand analysis (see /topics/circuit-analysis): deriving small-signal gain, bandwidth, poles and zeros, feedback stability and phase margin, and input-referred noise before any simulator is opened, then using the gm/Id methodology to map those targets onto real device sizes and bias points. Simulation and verification: running DC, AC, transient, and noise analyses in a SPICE-class simulator such as Spectre, then sweeping process-voltage-temperature corners and Monte Carlo mismatch to confirm the design holds across the manufacturing distribution, not just at the typical corner. Layout-aware design: working in a tool like Cadence Virtuoso so that matching, common-centroid placement, guard rings, and routing parasitics are part of the design intent rather than an afterthought handed to a layout engineer. Senior analog and mixed-signal designers are expected to connect block-level specifications to system consequences. A data converter's ENOB shortfall might trace to sampling kT/C noise, capacitor mismatch causing DNL, or reference settling that creates harmonic spurs; a PLL's failure to meet a phase-noise mask might come from a loop-bandwidth choice that exposes VCO noise or charge-pump mismatch that raises reference spurs. Isolating which mechanism dominates requires both device-level analysis and a system view of how the blocks interact.
Why interviewers ask
Feedback stability and small-signal analysis are the most common analog interview deep-dive because nearly every useful analog block — op-amps, regulators, PLLs — is a closed loop, and a designer who cannot reason about poles, zeros, and phase margin will build circuits that ring or oscillate in silicon. Interviewers do not expect a candidate to recall every transfer function from memory; they want to see the candidate sketch a Bode plot, identify the dominant pole, explain how Miller compensation splits the poles, and predict what a capacitive load does to phase margin. This separates designers who treat gain = gm times rout as the whole story from those who understand the dynamics that determine whether a loop is usable. Data-converter metrics are tested because ADCs and DACs are where analog imperfection becomes a measurable system spec, and product teams constantly ask why a converter misses its target ENOB or SFDR. The interview probes whether a candidate can map a metric back to a physical cause: a missing code (DNL) to capacitor or current-source mismatch, an SNR shortfall to quantization plus thermal and kT/C noise, an SFDR limit to switch nonlinearity or reference glitches. A candidate who can say which measurement would distinguish a noise-limited converter from a distortion-limited one is demonstrating the diagnostic skill the job actually requires. Noise, PLL design, and device-physics questions appear because they are where analog designers spend real effort and where shallow knowledge is easy to expose. Noise sets the resolution floor, so interviewers ask which source dominates a given stage and how device sizing trades it against power and bandwidth. PLL questions test whether a candidate can justify a loop-bandwidth choice against the spur, lock-time, and phase-noise trade-off rather than just naming the blocks. Device-physics questions — gm/Id sizing, channel-length modulation, body effect, Pelgrom mismatch — reveal whether the candidate reasons from a real bias point or only from ideal square-law equations.
Common mistakes
The most common mistake is reasoning only at the schematic level and ignoring layout parasitics and matching. A circuit that simulates perfectly on an ideal netlist can shift its dominant pole because of routing capacitance on a high-impedance node, lose accuracy because a current mirror was not laid out common-centroid, or pick up digital switching noise because a sensitive node lacked a guard ring and was routed next to a noisy bus. Strong analog designers treat layout as part of the circuit, expect the post-layout extracted netlist to behave differently from the schematic, and design matching and shielding deliberately rather than discovering parasitic problems after tape-out. A second common gap is memorizing data-converter metric definitions without understanding what degrades them. A candidate who can recite that ENOB is derived from SNDR or that SFDR is the largest spur, but cannot connect DNL to capacitor mismatch, SNR to kT/C and thermal noise, or harmonic spurs to sampling-switch nonlinearity, cannot actually debug a converter that misses spec. The same gap appears with PLLs — naming the phase detector, charge pump, and loop filter without explaining how loop bandwidth trades spur suppression against lock time and phase-noise filtering — and signals that the candidate has studied block diagrams rather than closed real loops. A third gap is ignoring process-voltage-temperature corners and device mismatch, and failing to reason intuitively about feedback stability. Candidates who validate a design only at the typical corner are surprised when it fails at slow-cold or fast-hot, where bias points, gain, and phase margin all move; robust analog design assumes Monte Carlo mismatch and full corner coverage from the start. Likewise, candidates who cannot explain phase margin physically — why roughly 60 degrees gives a well-damped response and what pushes a loop toward instability — will misjudge compensation. Treating stability, mismatch, and corners as afterthoughts is the pattern that distinguishes a student answer from a designer who has shipped silicon.
ADC and data-converter metrics: what each measures, its dominant physical cause, and the interview signal it sends
| Metric | What it means | Dominant physical cause | Interview signal |
|---|---|---|---|
| INL | Accumulated deviation of code transitions from the ideal straight line, in LSB | Integrated DNL: capacitor or current-source mismatch summed across the array, plus reference and gain bending | Knows INL is the running sum of DNL and bends the overall transfer curve, not a per-code error |
| DNL | Per-code step-width error from the ideal 1 LSB, in LSB | Local element mismatch (capacitor or current source); -1 LSB is a missing code, a large negative DNL goes backward and breaks monotonicity | Distinguishes a missing code (DNL of -1 LSB) from a non-monotonic step (large negative DNL) and knows +/-1 LSB guarantees no missing codes |
| SNR | Signal power over total noise power, excluding harmonics, in dB | Quantization noise (6.02N + 1.76 dB) plus thermal and sampled kT/C noise | Separates the quantization floor from thermal and kT/C noise and sizes the sampling capacitor to a target SNR |
| SNDR | Signal power over noise plus distortion power, in dB | Noise sources of SNR plus harmonic distortion from sampling-switch and amplifier nonlinearity | Watches how SNDR moves with input amplitude and sample rate to tell a noise-limited part from a distortion-limited one |
| ENOB | Effective number of bits, derived as (SNDR - 1.76) / 6.02 | Whatever limits SNDR: the larger of the noise floor and the distortion floor | Derives ENOB straight from SNDR rather than treating it as an independent spec |
| SFDR | Ratio of the signal to the largest spur, in dB or dBc | The single largest spur: a harmonic from sampling-switch nonlinearity or a reference-settling glitch | Maps SFDR to a specific spur mechanism instead of lumping it with broadband noise |
Frequently asked questions
- What small-signal analysis questions reveal whether an analog designer understands feedback stability rather than just reciting gain formulas?
- Interviewers ask a candidate to find the dominant pole of a multi-stage amplifier and explain how it sets the gain-bandwidth product, then push on what happens to phase margin when a second pole moves toward the unity-gain frequency. A strong answer connects the pole/zero locations to a Bode plot, explains why roughly 60 degrees of phase margin is the usual target for a well-damped step response, and describes Miller compensation as deliberately splitting the poles so the dominant pole drops and a feedforward zero is managed. Weak candidates quote gain = gm times rout but cannot say what makes the loop ring or oscillate, or why adding a load capacitor on an unbuffered op-amp can erode phase margin and cause instability.
- How do interviewers probe whether a candidate truly understands ADC metrics like INL, DNL, SNR, SNDR, ENOB, and SFDR?
- Definitions are easy to memorize, so interviewers ask what physically degrades each metric. A DNL of -1 LSB means a missing code — a code whose width collapses to zero — usually from capacitor or current-source mismatch in the converter array; a large negative DNL (a step that goes backward) is what causes non-monotonicity, while a large positive DNL widens a code without by itself breaking monotonicity, and keeping DNL within +/-1 LSB guarantees no missing codes. INL is the accumulated DNL and bends the transfer curve. SNR is bounded by quantization noise (6.02N + 1.76 dB) plus thermal and sampling kT/C noise, while SNDR folds in distortion, and ENOB is derived directly from SNDR. SFDR is set by the largest spur, often a harmonic from sampling-switch nonlinearity or a reference-settling glitch. A strong candidate explains how to separate a thermal-noise-limited converter from a distortion-limited one by looking at how SNDR moves with input amplitude and sample rate, rather than treating the metrics as independent line items.
- What PLL and VCO interview questions separate candidates who have closed a loop from those who only know the block diagram?
- Interviewers ask a candidate to choose a loop bandwidth and justify it against the trade-off between reference spur suppression, lock time, and phase-noise filtering. A strong answer explains that the loop bandwidth is the crossover where VCO phase noise (which the loop suppresses below the bandwidth) hands off to reference and divider noise (which dominates inside the bandwidth), so widening the loop speeds lock and filters VCO noise but lets more reference spur and charge-pump noise through. They discuss how reference spurs are implementation-dependent — driven by charge-pump up/down current mismatch, phase-frequency-detector dead zone, and (in fractional-N) quantization of the divider — the damping factor set by the loop filter zero, and how integer-N versus fractional-N changes the spur and quantization-noise picture. Naming the phase detector, charge pump, loop filter, VCO, and divider without these trade-offs is a shallow answer.
- Why do interviewers focus on noise — thermal, flicker (1/f), and sampled kT/C — in analog and mixed-signal interviews?
- Noise sets the lowest signal an analog front-end can resolve, so it is the limiting spec in most precision and RF designs. Interviewers ask a candidate to identify the dominant noise source in a given stage: thermal noise (a voltage PSD of 4kTR V^2/Hz for a resistor; for a MOSFET channel the input-referred voltage-noise PSD is approximately 4kT times gamma over gm in V^2/Hz, while the channel current-noise PSD is 4kT times gamma times gm in A^2/Hz) dominates at higher frequencies, while flicker 1/f noise dominates near DC and is why chopping and correlated double sampling exist. In switched-capacitor circuits, sampling kT/C noise sets the minimum capacitor size for a target SNR independent of resistance. A strong candidate computes input-referred noise, explains why increasing gm or device area trades power and bandwidth against noise, and connects noise figure in an RF LNA back to these same physical sources rather than treating NF as a standalone number.
- What layout and parasitic questions do analog interviews ask that schematic-only candidates miss?
- Interviewers ask how a candidate would lay out a differential pair or a current mirror for matching, expecting common-centroid placement to cancel linear process gradients, dummy devices at array edges, matched orientation, and guard rings to isolate substrate noise. They probe parasitics directly: routing capacitance on a high-impedance node that shifts a pole, IR drop on a supply rail that shifts a bias point, and bond-wire inductance that resonates with on-chip capacitance. A strong candidate treats layout as part of the circuit, reasons about post-layout extraction changing the simulated phase margin or settling, and explains why a sensitive node should be shielded and kept short. Candidates who only reason at the schematic level are surprised when the extracted netlist behaves differently from the ideal one.
- How do interviewers test the gm/Id design methodology and core device physics for analog designers?
- The gm/Id methodology lets a designer pick an operating region from a single efficiency number rather than guessing transistor sizes: high gm/Id (weak inversion, approximately 20-25 V^-1, the exact value being operating-point and process dependent) maximizes transconductance per unit current for low-power, low-frequency stages, while low gm/Id (strong inversion) gives higher fT for fast stages at the cost of current. Interviewers ask a candidate to size a device for a target gain and bandwidth and justify the inversion level chosen. They also probe second-order physics (see /topics/semiconductor-devices): channel-length modulation setting output resistance and intrinsic gain, body effect shifting threshold voltage in stacked devices, and Pelgrom mismatch where standard deviation scales inversely with the square root of device area, which forces large devices in matched references. Strong candidates use these to reason about a real bias point, not just ideal square-law equations.
- What bandgap reference and LDO questions reveal real analog design depth?
- For a bandgap, interviewers ask how a temperature-independent voltage is built: a PTAT term from the difference of two base-emitter voltages at different current densities is summed with the CTAT base-emitter voltage to cancel first-order temperature drift, landing near 1.2 V. A strong candidate discusses curvature correction for the residual second-order term, startup circuits to avoid the degenerate zero-current state, and op-amp offset as a dominant accuracy error. For an LDO, they reason about the pass-device dropout, the dominant pole created by the load and output capacitor, the ESR zero that can be used for compensation, power-supply rejection rolling off with frequency, and load-transient response governed by the loop bandwidth and output capacitance. These are the circuits where stability, noise, and accuracy intersect.
- What does mixed-signal verification test that pure analog or pure digital candidates underestimate?
- Mixed-signal verification asks how analog behavior is connected into a digital verification flow without simulating every transistor for millions of cycles. A strong candidate explains real-number modeling, where an analog block is abstracted as a discrete-time real-valued model (in Verilog-AMS wreal or SystemVerilog real nets) so the digital simulator can run fast functional regressions, and contrasts it with full AMS co-simulation that couples a SPICE-class analog solver to the digital engine for accuracy at the cost of speed. They discuss verifying the analog-digital interface: level shifting across power domains, clock-domain crossing into the data converter, and substrate or supply noise coupling. They also cover PVT corners and Monte Carlo runs in Spectre or SPICE to confirm mismatch and process spread do not break the interface, since a block that passes typical-corner simulation can still fail at a slow-cold or fast-hot corner.
- What RFIC-specific questions should I expect, and what does a strong answer cover?
- RFIC interviews move from baseband analog into the radio front-end, so expect S-parameters and impedance matching on the Smith chart, and the distinction between a noise match and a power match in an LNA — the source impedance that minimizes noise figure is generally not the conjugate match that maximizes power transfer, so the designer trades a small noise penalty for gain and stability. Expect linearity questions on IIP3 and IIP2 and the P1dB compression point, mixer fundamentals (conversion gain, noise, linearity, and LO leakage and LO self-mixing creating DC offset), and power-amplifier efficiency versus linearity (class-A through class-AB and the back-off needed for a modulated signal). Strong candidates connect reciprocal mixing — where local-oscillator phase noise mixes a strong adjacent blocker onto the wanted channel — and blocker-driven desensitization back to the receiver noise and linearity budget, rather than treating each metric in isolation.
- What does a strong versus weak analog design answer sound like?
- A weak answer recites gain = gm times rout or replays memorized metric definitions (ENOB comes from SNDR, SFDR is the largest spur) without saying what sets or breaks them. A strong answer reasons about the dominant pole and phase margin, maps a spec miss to a physical cause — capacitor or device mismatch, sampled kT/C noise, charge-pump spurs on a PLL — and names the measurement that separates a noise-limited part from a distortion-limited one, such as watching how SNDR moves with input amplitude and sample rate. The strong candidate treats every number as the visible symptom of a device-level or layout-level mechanism.
- How should I practice for an analog / mixed-signal / RFIC interview?
- Drill the hand-analysis skills interviewers actually test: analyze a two-stage amplifier on paper and sketch its Bode plot to find the dominant pole and phase margin, size a sampling capacitor for a target SNR from the kT/C noise limit, derive ENOB from a given SNDR, choose a PLL loop bandwidth and justify it against the spur, lock-time, and phase-noise trade-off, and reason through the LNA noise-figure versus linearity tradeoff including the noise-match versus power-match choice. Practicing these on paper, then confirming intuition against a SPICE-class simulation, builds the reasoning a strong answer demonstrates.
Related topics
Essential AI-Native Skills for Analog, Mixed-Signal & RFIC Design Interview Questions
Modern engineering work increasingly uses AI tools for design and code review, debugging, documentation, test and testbench generation, and workflow automation. The goal is not to let AI replace engineering judgment — it is to move faster while keeping verification discipline.
- Use AI to explain unfamiliar code, logs, waveforms, datasheets, or test failures.
- Break large problems into small, reviewable steps you can verify independently.
- Ask AI for hypotheses, then validate them against tests, measurements, simulations, or lab data.
- Version-control your analysis scripts, testbenches, and configs — keep changes small and reviewable.
- Document your assumptions, design tradeoffs, and debugging decisions.
- Verify AI output before trusting it: run the checks that fit the domain — unit tests, linters, simulations, or bench/lab measurements.
- Review AI output for correctness, edge cases, and real-world consequences.