CPO vs Pluggable Optics: Density, Power & AI-Cluster Trade-offs Interview Prep

Pluggables vs NPO vs CPO — Architectural Trade-offs

Sample interview questions

1. Why are hyperscale AI training clusters driving the migration from pluggable optics to CPO (co-packaged optics)?
   • A. CPO and pluggables are equivalent; the choice is preference.
   • B. AI training clusters need extreme bandwidth between thousands of GPUs/TPUs (typical 800G-3.2T per GPU pair). Pluggables are limited by faceplate area (a 1U switch can fit only so many QSFP-DD/OSFP modules) and SerDes/PCB length (electrical signals degrade over inches at 100+ Gbps). CPO eliminates these by integrating optics on the same package as the host ASIC — optical I/O leaves the chip directly, no electrical-to-optical conversion across PCB traces. This enables higher per-port bandwidth, more ports per ASIC, and lower power per bit. The trade-off: pluggables are field-replaceable; CPO requires the whole ASIC+optics package to be swapped if any optical channel fails. ✓
   • C. CPO uses copper instead of optics.
   • D. CPO is only used in submarine systems.

   Option B is correct. AI cluster networks have radically different bandwidth and density requirements than traditional datacenter switching: **Bandwidth scale**: a single AI GPU in 2026 needs 800 Gb/s to 1.6 Tb/s of inter-GPU bandwidth for training-time parameter exchange. A 1024-GPU cluster needs ~1 Pb/s of aggregate fabric bandwidth. Per-server PCIe and per-rack switching cannot keep up; the network fabric becomes the bottleneck. **Faceplate limits**: a standard switch chassis can fit ~64 OSFP modules in 1RU (or 36-48 QSFP-DD in 1RU). At 800G per module, that's 51 Tb/s aggregate switching bandwidth per RU. Beyond that, faceplate density is the binding constraint. **SerDes/PCB length**: at 100+ Gbps per lane, the electrical signal can only travel inches before requiring retimers or losing significant SNR. Modern switch ASICs have 100+ ports of 100+ Gbps SerDes; each lane requires either short PCB routing (constraining package size) or retimers (adding power). **CPO addresses both**: the optical I/O leaves the chip directly via co-packaged silicon-photonics dies. No long electrical traces, no retimers, no QSFP/OSFP form-factor constraints. Per-port density can be 2-4× higher than pluggables. **The downsides**: - **Serviceability**: pluggables are field-swappable when they fail. CPO failure of any optical channel requires the whole ASIC+optics package to be swapped — a much more disruptive operation. Vendors are working on partial-FRU (field-replaceable unit) approaches. - **Power thermal**: CPO co-locates optical dissipation with the high-power ASIC. Thermal management is harder. - **Manufacturing**: CPO assembly is more complex than pluggable manufacturing — fewer suppliers, lower-volume yield curves. **Production timeline**: pre-production CPO appears in select hyperscaler AI clusters in 2024-2025; broader commercial deployment in 2026-2027. Pluggables remain dominant for non-AI datacenter switching and for any application where serviceability matters more than density. Option A misses the AI-cluster driver. Option C confuses CPO with copper interconnect. Option D is unrelated.

2. A datacenter operator considers NPO (near-packaged optics) as a middle-ground between pluggables and CPO. What does NPO mean, and what trade-off does it offer?
   • A. NPO is the same as CPO; the names are synonyms.
   • B. NPO places the optics in a separate optical-engine package mounted very close to (but not on) the host ASIC — typically on the same PCB within 1-2 inches. The optical engine is connected to the ASIC via short electrical traces or interposers. NPO captures most of the density and bandwidth benefits of CPO without the full integration complexity: the optical engine is its own FRU separate from the ASIC, manufacturing is simpler, and thermal management is decoupled. The trade-off: NPO has slightly more electrical loss and PCB constraints than CPO, but is much more practical to deploy and service. ✓
   • C. NPO is an older form of pluggable.
   • D. NPO is only used at FR2 frequencies.

   Option B is correct. NPO (Near-Packaged Optics) is the architectural compromise between pluggables and CPO: **Pluggables (e.g., OSFP, QSFP-DD)**: optics in a hot-swappable module at the faceplate, connected to the ASIC via PCB traces (typically 3-6 inches). Easy to service, but density-limited by faceplate area and SerDes reach. **NPO**: optics in a separate package mounted on the PCB within 1-2 inches of the ASIC. Connected via short PCB traces or silicon interposer. The optical engine is field-replaceable but as a larger unit than a single transceiver. Captures most density/bandwidth benefits of CPO. **CPO (Co-Packaged Optics)**: optics integrated on the same package substrate as the ASIC — typically via 2.5D silicon interposer with optical I/O dies adjacent to the ASIC. Best density and bandwidth, but optics are not separately replaceable. The progression from pluggable to NPO to CPO: - Decreasing electrical-trace length (better signal integrity at high baud rates) - Increasing per-port density - Decreasing power per bit (no long PCB transmission) - Decreasing serviceability (smaller field-replaceable unit) NPO's value proposition: nearly all the technical benefits of CPO with practical serviceability. NPO products from companies like Broadcom (CPO 1.0 was effectively NPO), Cisco, and Lightmatter offer this middle-ground. Deployment reality: as of 2026, most "CPO" production deployments are technically NPO. True per-die CPO is emerging but assembly complexity limits volume. Many hyperscalers are deploying NPO first as a stepping-stone toward eventual true CPO. Option A collapses real architectural differences. Option C confuses NPO with pluggable form factors. Option D is unrelated to deployment frequency.

Frequently asked questions

What is CPO (co-packaged optics)?

CPO is the architecture where optical transceivers are integrated on the same package as the host ASIC (switch ASIC, GPU, AI accelerator). The optical I/O leaves the chip package directly via fiber pigtails, eliminating the long PCB traces and pluggable form-factor constraints that limit traditional architectures. CPO enables higher per-port bandwidth, more ports per ASIC, and lower power per bit. The trade-off: optics are not field-replaceable as a separate module — a failed optical channel requires swapping the entire ASIC+optics package. CPO is increasingly deployed in hyperscale AI training clusters where bandwidth density requirements exceed what pluggables can deliver.

How does CPO compare to pluggables?

Pluggables (OSFP, QSFP-DD, QSFP112) are hot-swappable modules at the switch faceplate, connected to the ASIC via PCB traces. Strengths: field-replaceable per transceiver, mature manufacturing, supply-chain flexibility, simple thermal management. Limitations: faceplate density caps total switch bandwidth, electrical-trace length penalty at 100+ Gbps SerDes, higher power per bit due to long PCB transmission. CPO eliminates these by integrating optics on the ASIC package, but at the cost of serviceability and manufacturing complexity. The decision is application-specific: pluggables for standard datacenter switching, CPO for AI clusters where density binds.

Why do AI training clusters drive CPO adoption?

AI training requires extreme bandwidth between thousands of GPUs/TPUs for parameter exchange — a single GPU in 2026 typically needs 800G-1.6T of inter-GPU bandwidth, and a 1024-GPU cluster needs ~1 Pb/s aggregate fabric bandwidth. Pluggables are limited by switch faceplate area (a 1RU switch fits 64 OSFP modules max), SerDes/PCB reach (100+ Gbps signals only travel inches before retimers), and per-port power. CPO bypasses these limits by integrating optics with the ASIC, enabling 2-4× higher per-port density and lower power per bit. The economic driver: as AI cluster sizes scale, pluggable-based fabrics become physically impractical and CPO becomes necessary.

What is NPO (near-packaged optics)?

NPO is the architectural middle-ground between pluggables and CPO. The optics are in a separate package mounted very close to the host ASIC — typically on the same PCB within 1-2 inches — connected via short PCB traces or silicon interposer. The optical engine is field-replaceable as a separate unit (larger than a single transceiver but smaller than the whole ASIC). NPO captures most of the density and bandwidth benefits of CPO while preserving serviceability. As of 2026, most "CPO" production deployments are technically NPO; true per-die CPO is emerging but assembly complexity limits volume.

What is the serviceability difference between pluggables and CPO?

Pluggables are hot-swappable per transceiver: a single failed optical port can be replaced in seconds without disrupting the rest of the switch. This is the standard datacenter operations model and the reason pluggables remain dominant for most applications. CPO has no field-replaceable unit smaller than the ASIC+optics package — a single failed optical channel requires swapping the entire package, which is a much more disruptive operation. NPO sits in the middle: the optical engine is field-replaceable but as a larger unit than a single transceiver. The serviceability question is one of the major reasons CPO adoption is concentrated in AI clusters where uptime can tolerate the trade-off; mainstream datacenter operators still prefer pluggables.

How do pluggable form factors evolve (QSFP-DD, OSFP, OSFP-XD)?

Pluggable form factors evolve to support higher per-port bandwidth: QSFP+ (40G), QSFP28 (100G), QSFP-DD (400G), QSFP112 (400G+ with single-die SerDes), OSFP (400G/800G with thermal headroom), OSFP-XD (1.6T+). The progression adds power dissipation capability (more thermal headroom), more electrical lanes, and faster per-lane SerDes. QSFP-DD has 8 lanes at 50G each (PAM-4); OSFP has 8 lanes at 100G each. The form factor choice depends on density per RU (QSFP-DD packs denser), thermal capability (OSFP handles higher dissipation), and ecosystem maturity (QSFP-DD is more established). Both QSFP-DD and OSFP coexist in 2026 deployments; OSFP is gaining at higher bandwidth where its thermal headroom matters.

How does CPO affect power per bit?

CPO reduces power per bit by eliminating long electrical transmission. In pluggables, the signal travels through PCB traces (3-6 inches), through the QSFP-DD/OSFP connector, and through cable assemblies — each segment has loss and noise that requires either equalization (consuming power) or higher transmit power (also consuming power). CPO co-locates the optical engine with the ASIC, so the electrical signal only crosses millimeter-scale traces or silicon interposer paths. The power saving is roughly 30-50% per bit at 800G+ — significant when multiplied across thousands of switch ports in an AI cluster. The thermal payoff matters too: lower total power means simpler cooling design.

What is the SiPh role in CPO?

CPO requires very compact, high-density, low-power optical engines — exactly what silicon photonics is engineered to deliver (see /topics/silicon-photonics-datacenter). Most CPO architectures use SiPh dies for the modulator + photodetector functions, with InP lasers (either externally coupled via fiber or hybrid-bonded). The CMOS-compatible nature of SiPh enables co-fabrication with the ASIC die or co-packaging on the same substrate. Ring modulators are the typical CPO choice because of their compact footprint (10-50 μm vs mm for MZM), at the cost of thermal-tuning power. The integration question for CPO: SiPh+InP-laser via hybrid bonding (Intel approach), SiPh+external laser via fiber pigtail (most common), or SiPh+integrated quantum-dot laser (emerging research).

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