Interview Prep Topics

Bluetooth versions and BLE generations compared for interview prep: Classic BR/EDR vs Low Energy, what 4.0 / 4.2 / 5.0 / 5.1 / 5.2 / 5.4 / 6.0 each changed, PHYs, LE Audio, and Channel Sounding.

RTL design interview prep for ASIC and FPGA: Verilog/SystemVerilog, FSMs, clock domain crossing, async FIFOs, blocking vs non-blocking, timing closure, and synthesizable coding.

The digital ASIC design flow explained for interviews — spec, RTL, verification, synthesis, DFT, physical design (place & route), STA, signoff (DRC/LVS), and tapeout, plus front-end vs back-end and ASIC vs FPGA.

5G NR RRC states explained — RRC_IDLE, RRC_INACTIVE, RRC_CONNECTED transitions, RAN Notification Area, paging, and power saving trade-offs.

5G NR initial access — SSB cell search, MIB and SIB1 decode, 4-step vs 2-step RACH, contention resolution, and open-loop power control.

5G NR physical channels — PDCCH and CORESET, PDSCH allocation, PUCCH formats, PUSCH grant types, RNTI types, DCI families, and UCI multiplexing.

5G NR reference signals — DMRS channel estimation, CSI-RS for CSI and beam management, SRS uplink sounding, PTRS phase tracking, and the SSB.

5G NR beam management — SSB beam sweep, P-1/P-2/P-3 refinement, TCI states and activation, QCL types, and beam failure recovery.

5G NR BWP and numerology — subcarrier spacing μ=0..4, FR1 vs FR2, frame/slot structure, resource grid, BWP switching, and CP overhead.

Coherent optical detection explained — local oscillator, 90° hybrid, balanced photodiodes, DSP pipeline, LO linewidth, and intradyne reception.

DWDM systems explained — ITU-T frequency grid, 50 GHz vs 100 GHz spacing, C-band vs L-band, flex-grid, superchannels, and 400ZR/800ZR pluggable optics.

EDFA vs Raman vs SOA compared: gain mechanism, noise figure, bandwidth, and where each optical amplifier fits in long-haul, distributed, and integrated systems.

Mach-Zehnder modulators explained: the electro-optic effect, Vπ, push-pull drive/bias point, and chirp — how optical transmitters encode symbols in coherent links.

Coherent modulation formats explained: DP-QPSK, DP-16QAM, 64QAM, and probabilistic constellation shaping — bits per symbol, reach, and the OSNR trade-off.

ITU-T optical fiber standards explained — G.652 single-mode workhorse, G.654 submarine large-Aeff, G.657 bend-insensitive, hollow-core for low latency.

5G NR handover — Xn vs N2 signaling paths, conditional handover, measurement events A1-A6, time-to-trigger, MRO, and intra/inter-DU mobility.

5G NR MAC scheduling — SR and BSR uplink-grant request, DRX power saving, configured grant Type 1 vs Type 2, MAC CE control, and scheduler trade-offs.

5G NR channel coding — LDPC for PDSCH/PUSCH data, polar codes for PDCCH/PUCCH control, MCS tables, CQI link adaptation, OLLA, and HARQ incremental redundancy.

OSNR, BER, and Q-factor in optical engineering — pre-FEC vs post-FEC BER, FEC limit, OSNR margin, shot vs thermal noise, and how operators measure link health.

Optical fiber impairments explained: chromatic dispersion, PMD, attenuation, and Kerr nonlinearities (SPM, XPM, FWM) — how each limits reach; coherent DSP fixes CD/PMD while FEC and power design handle the rest.

ROADMs explained: how wavelength-selective switches (WSS) add/drop and route wavelengths, and what "degrees" and colorless-directionless-contentionless (CDC) mean.

5G NR architecture — NSA Option-3 EN-DC vs SA Option-2, dual connectivity, CU/DU split, F1 interface, carrier aggregation, and 5GC functions.

5G QoS framework — 5QI table, GBR vs non-GBR, packet delay budget, packet error rate, QoS flows, DRB mapping via SDAP, and slicing integration.

URLLC in 5G NR — mini-slot scheduling, preemption indication, MCS Table 3, PDSCH/PUSCH repetition, configured grant, and 1 ms latency at 10⁻⁵ reliability.

3GPP 5G release evolution — Rel-15 NR foundation, Rel-16 URLLC and IIoT, Rel-17 RedCap and NTN, Rel-18 5G-Advanced with AI/ML and MBS.

Silicon photonics for datacenters explained: CMOS-compatible modulators, waveguides, and dense integration enabling 800G/1.6T pluggable, coherent, and co-packaged optical engines.

Co-packaged optics (CPO) put the optical engine on the switch ASIC — ~30–50% less power-per-bit than pluggable QSFP-DD/OSFP, but harder to service. CPO vs NPO vs pluggable.

PON architectures from GPON to 50G-PON — OLT, ONU, splitter, burst-mode receivers, dynamic bandwidth allocation, TWDM-PON, and the 50G upgrade.

Silicon photonics engineer interview signals — device design, thermal management, CMOS-compatible fab, laser integration, CPO architecture, production test.

Master AI agent architecture for interviews: 4-layer system design, loop patterns (ReAct, planner-executor), multi-agent trade-offs, observability, and production safety.

MCP interview prep — client-server architecture, tools vs resources vs prompts, capability negotiation, transports, auth boundaries, A2A distinctions, and production patterns.

LLM evaluation best practices — eval harness design, Self-Refine, DSPy compile, reward hacking detection, rubric scoring, regression gates, and CI-driven improvement loops.

RAG for engineers — ground LLM answers in technical specs, datasheets, and 3GPP/IEEE standards: hybrid retrieval, RRF, chunking, citation markers, faithfulness evaluation, Self-RAG, and RAG vs KB-Routing.

Vector databases and embeddings for AI engineers: semantic search, HNSW vs IVF indexing, chunking strategy, hybrid search, reranking, pgvector, and vector-vs-graph trade-offs.

Structured output and tool calling best practices — six-technique ladder, schema design, validate-and-retry, Instructor vs native structured outputs, and production pitfalls.

AI agent observability interview prep: span trees, OpenTelemetry GenAI conventions, production drift types, sampling strategy, and tool selection for senior engineers.

When to use RAG, KB-Routing, fine-tuning, or the hybrid route-then-RAG pattern — decision framework, trade-off comparison table, and production pitfalls.

Open RAN (O-RAN) interview prep — disaggregated architecture, Near-RT RIC, xApps, rApps, Open Fronthaul, and RAN intelligence for interview questions.

Near-RT RIC vs Non-RT RIC for interview prep — real-time vs strategic RAN decisions, xApps, rApps, A1 interface, and RAN intelligence control.

O-RAN split 7.2x interview prep — Open Fronthaul, RU-DU interface, latency, bandwidth, IQ sample transport, and deployment trade-offs.

O-RAN interfaces explained: A1 carries policy from the Non-RT to the Near-RT RIC, E2 gives near-real-time control of the CU/DU, O1 handles management, and O2 manages the O-Cloud.

Open RAN vs traditional RAN for interview prep — monolithic vs disaggregated, vendor lock-in, cost, interoperability, and operator strategy.

xApps and rApps for interview prep — Near-RT vs Non-RT RIC, the three O-RAN control loops, E2/A1/R1 interfaces, KPM telemetry, and ML-driven RAN optimization.

O-RAN energy efficiency for interview prep — cell sleep/wake, power scaling, traffic prediction, ML-driven optimization, and operator sustainability goals.

AI-powered interview prep for engineers — adaptive practice, personalized learning, spaced repetition, and how to choose the right AI tutoring platform.

How engineers use AI for interview prep without the over-reliance trap: the attempt-feedback-retest loop, held-out progress signals, and what to say about AI use in the interview.

How AI tutors for engineering interview prep actually work — learner models, retrieval practice, spaced review, hallucination, and how to tell if one is improving your skills.

IEEE 802.11 wireless standards for engineers: 802.11n/ac/ax/be/bn, Wi-Fi 4 through Wi-Fi 8, OFDMA, MU-MIMO, MLO, EMLSR, NPCA, 6 GHz.

RF engineering industry gap: link budgets, antennas, noise figure, impedance matching, lab measurements, spectrum issues, and debugging.

Wi-Fi 8 and 802.11bn UHR: reliability, latency, mobility, interference, coordinated APs, MLO, spectrum reuse, and standards tradeoffs.

Wireless engineering industry gap: OFDM, MIMO, 5G NR, Wi-Fi, modem logs, fading, link budgets, simulations, and field testing.

RTL design industry gap: Verilog, SystemVerilog, synthesis, timing, CDC, resets, microarchitecture, verification, and SoC tradeoffs.

Firmware industry gap: C, RTOS, interrupts, DMA, drivers, memory limits, hardware interfaces, debugging, and product constraints.

FPGA industry gap: RTL, timing closure, CDC, testbenches, simulation, pipelining, BRAM, DSP slices, and hardware debugging.

What RF engineer interviews test: RF chain debugging, link budgets, noise figure cascades, impedance matching, lab measurement judgment, antenna-in-place, and certification.

RTL design engineer signals: Verilog, SystemVerilog, microarchitecture, timing closure, CDC, synthesis, verification, and SoC tradeoffs.

Modem engineer interview signals: LTE, 5G NR, RRC, PHY, MAC, attach failures, handover, throughput, modem logs, and field testing.

Optical engineer interview signals: the systems-level reasoning interviewers probe — link budgets, OSNR, coherent DSP, ROADM architecture, and 400ZR/800ZR trade-offs.

Integration engineer interview signals: multi-IP/SoC integration, RF+PHY+MAC+firmware bring-up, lab instrument triage, and cross-domain HW/FW debugging.

Pre-silicon vs post-silicon explained: how verification, validation, bring-up, and integration engineering roles differ across the chip development lifecycle.

What analog, mixed-signal, and RFIC design interviews test: transistor-level design, ADC/DAC, PLL, noise, layout parasitics, RFIC blocks, and mixed-signal verification.

What SoC design engineer interviews test: SoC architecture, IP integration, on-chip interconnect/buses, clocking and reset, power management, and hardware/software partitioning.

The ASIC physical design / backend flow explained for interviews: floorplanning, placement, CTS, routing, static timing analysis, and signoff (DRC/LVS/IR drop).

DFT explained for interviews: scan chains, ATPG, fault models, test coverage, MBIST, boundary scan (JTAG), and how design-for-test trades area for testability.

ATE and semiconductor production test for interviews: test-program development, wafer sort vs final test, yield, binning, guardbanding, cost-vs-coverage, and DFT/ATPG/BIST.

Python for hardware, RF, silicon, and test interviews — PyVISA/SCPI instrument control, numpy/pandas log analysis, lab and CI automation, and what hardware interviewers expect you to DO with it.

Bench debug for hardware/RF/validation interviews: scope bandwidth vs sample rate (0.35/tr), probe loading, logic analyzer, spectrum analyzer, VNA S-parameters, and power-on bring-up.

CUDA & GPU programming for engineers — threads/warps/blocks and SIMT, the memory hierarchy, coalescing, occupancy, host-device transfer, and when GPU acceleration actually helps.

Embedded serial protocols for interviews — I2C (open-drain, pull-ups, clock stretching), SPI (4-wire, CPOL/CPHA modes, chip-select), UART (async framing, baud, flow control), and bring-up debug gotchas.

Low-power digital design for interviews: dynamic vs leakage power, clock gating, power gating (sleep transistors), multi-Vt, DVFS, power/voltage domains, isolation/level-shifter/retention cells, and UPF/CPF power intent.

Chiplets, UCIe die-to-die links, advanced packaging (2.5D interposers, 3D stacking, HBM), and CXL cache-coherent memory over PCIe — explained for SoC, systems, and packaging interviews.

DDR memory interface interview prep: DDR vs LPDDR vs GDDR vs HBM, the controller and DDR PHY, write/read leveling and training, the DFI interface, SI, and bandwidth/latency.

What UVM verification interviews test: testbench architecture (agent/driver/monitor/sequencer/scoreboard), constrained-random, functional coverage, phases, and SystemVerilog OOP.

The Verilog/SystemVerilog interview questions RTL candidates actually get: blocking vs non-blocking, synthesizable RTL, FSMs, CDC, FIFOs, and reset/clocking.

STA explained for interviews: setup vs hold, slack, arrival/required time, clock skew/uncertainty, MCMM, OCV/AOCV, and how to read a timing report.

What embedded engineer interviews test: C and memory, ISRs and concurrency, peripherals (I2C/SPI/UART), RTOS vs bare-metal, debugging, and the hardware/software boundary.

How MATLAB and Simulink are used in wireless/DSP interviews and work: link simulation, BER/EVM, channel models, FIR/IIR filters, fixed-point, and Simulink modeling.

How multiple radios coexist in one device: in-device coexistence (Wi-Fi 802.11 + Bluetooth in 2.4 GHz), desense, PTA arbitration, antenna isolation, and cellular coexistence.

What RF engineers actually do: antennas, RF chains, link budgets, noise figure, impedance matching, lab testing, wireless systems, and debugging.

Wi-Fi standards interview questions and answers for engineers — 802.11ax (Wi-Fi 6), 802.11be (Wi-Fi 7), 802.11bn (Wi-Fi 8), OFDMA, MLO, AFC, coexistence.

OFDMA resource units in IEEE 802.11ax (Wi-Fi 6) and 802.11bn (Wi-Fi 8): 26 to 996-tone RUs, RRU vs DRU vs MDRU, scheduling, and OFDMA vs MU-MIMO.

Multi-Link Operation (MLO) — the Wi-Fi 7 (802.11be) / Wi-Fi 8 (802.11bn) feature that lets one MLD use several bands at once, cutting latency.

IEEE 802.11 amendment letters name each Wi-Fi standard; the Wi-Fi Alliance renames them: 802.11ax = Wi-Fi 6, 802.11be = Wi-Fi 7, 802.11bn = Wi-Fi 8.

IEEE 802.11bp Ambient Power Communications: harvested-energy Wi-Fi for battery-free IoT, backscatter modulation, 10^3 ppm clock tolerance, contrast with 802.11ah.

LDPC codes in wireless interview prep — Tanner graphs, belief propagation, min-sum decoding, 5G NR base-graph + lifting, Wi-Fi 6+ adoption, vs Polar codes.

PAPR interview prep — why OFDM has high PAPR, PA back-off cost, reduction techniques (clipping, tone reservation, SLM/PTS, DFT-s-OFDM), and 4096-QAM impact.

EVM interview prep — definition, % rms vs dB conventions, MCS-driven targets, transmitter and receiver sources (phase noise, IQ, PA, LNA), Wi-Fi 7 (802.11be) / 4096-QAM impact.

What industry expects from RF, wireless, firmware, FPGA, and RTL engineers beyond classroom theory — measurement discipline, cross-layer debugging, and product judgment.

Build a production AI agent: 4-layer architecture, tool schemas, stop conditions, message-history pitfalls, and framework graduation — interview-ready depth.

LLM structured output extraction — 5 constraint techniques, validate-and-retry, Instructor vs BAML vs Outlines vs native structured outputs, and production document pipelines.

LLM routing and caching for production — 5 routing axes, 4 cache layers, cascade routing, cache stampedes, and AI gateway selection for interview prep.

LLM guardrails and safety — defense-in-depth 3-tier model, NeMo vs LLM Guard vs Llama Guard 4, indirect prompt injection, canary tokens, and red-teaming with Garak and PyRIT.

Knowledge graphs for AI — property graphs vs RDF, GraphRAG vs vector RAG, entity resolution, temporal KGs, and production pitfalls. Interview prep.

Production AI agent control loops — ReAct, Plan-and-Execute, Tree of Thoughts, Reflexion, parallel tool dispatch, durable execution, sandboxing, MCP and A2A protocols.

Human-in-the-loop and dataset curation for production AI — five HITL patterns, active learning, golden-set versioning, and annotation tools for interview prep.

Adversarial critique for AI evals — critic prompt flavors, sycophancy prevention, round-table roles, specialist classifiers, and red-teaming with PyRIT and Garak.

How RF, hardware, and embedded engineers use AI dev tools, agentic workflows, and LLM/ML foundations on real projects — a structured guide, not a beginner chatbot tutorial.

How large language models actually work, for engineers: tokens, context windows, training vs inference, why they hallucinate, and where they are reliable.

Machine learning concepts for engineers: training vs inference, overfitting, data leakage, train/validation/test splits, metric choice, and when ML is the right tool.

Prompt engineering for technical work: structured prompts (goal, context, examples, output format, done criteria), few-shot, structured output, and what prompting cannot fix.

Using AI for engineering documentation: drafting specs, API docs, and runbooks from source, summarizing design discussions, preventing doc drift, and verifying before publishing.

Using AI for data analysis and scripting: parsing, transforms, queries, log triage, and quick scripts — grounded in real data, verified on a sample, computed with code.

Neural networks explained for engineers: units and weighted sums, activation nonlinearity, layers and depth, loss and gradient descent, backpropagation, overfitting, and when not to use one.

When NOT to use AI in engineering: tasks you cannot verify, exact-correctness needs, safety/security/regulated decisions, the verification-cost trap, and genuinely novel problems.

AI pair programming best practices: working with a coding assistant in small reviewed increments, staying the navigator, when to take over, and avoiding the autopilot trap.

How to evaluate and choose an AI coding tool: trial on your real tasks, weigh context handling, verification cost, failure modes, data privacy, and team fit over demos and benchmarks.

5G network slicing for interviews — S-NSSAI (SST/SD), Requested/Allowed/Configured NSSAI, NSSF slice selection, RAN/Core/transport realization, isolation, NSMF/NSSMF management.

Non-Terrestrial Networks (NTN) interview prep — satellite 5G (GEO/MEO/LEO/HAPS), 3GPP NR-NTN and IoT-NTN, transparent vs regenerative payload, delay, Doppler, GNSS pre-compensation.

Edge AI and model quantization explained for embedded engineers — INT8 vs FP32, PTQ vs QAT, per-channel and static quantization, pruning and distillation, and the memory/latency/accuracy tradeoff on MCUs and NPUs.

SystemVerilog for verification explained for interviews — the OOP testbench subset behind UVM: classes, constrained-random (randomize), functional coverage (covergroups), SVA assertions, interfaces, clocking blocks, and virtual interfaces.

Embedded Linux and device driver development explained for interviews — kernel vs user space, the driver model (character/block/network), device tree, the boot chain, cross-compilation, and Linux vs RTOS vs bare-metal.

ARM Cortex architecture for embedded interviews — Cortex-M vs A vs R profiles, the Cortex-M exception model and NVIC, MPU vs MMU, Thumb-2, privilege modes (MSP/PSP), and TrustZone.

RFIC design interview signals for RF integrated circuit engineers — on-chip LNA, mixer, PA, and VCO/PLL block design, cascaded NF/IP3 (Friis), noise-vs-power match, and the silicon-vs-board distinction.

C/C++ for embedded interviews — the memory model, pointers, volatile vs const, bit manipulation with masks, ISR-safe code, fixed-point Q formats, and why malloc is avoided in firmware.

Ethernet PHY interview prep: the IEEE 802.3 PCS/PMA/PMD stack, RS-FEC (KR4/KP4), PAM4 lanes, PMD naming for 100G/400G/800G, alignment markers, and Clause 73/72 link training.

How telecom, wireless, RF, and firmware engineers use AI coding assistants, agentic log triage, and spec-retrieval RAG — with the judgment to know when AI helps vs hurts.

The math that matters for machine learning and MLE interviews — linear algebra, probability and statistics, calculus, and optimization — with intuition over rote formulas.

PLL interview prep: PFD, charge pump, loop filter, VCO, divider; type-I vs type-II, loop bandwidth, integer-N vs fractional-N, spurs, and LO/clock synthesis.

LNA design for RF interviews: Friis cascade and first-stage noise, noise vs power match, source degeneration, common-gate, IIP3/P1dB linearity, and k-factor stability.

PA classes A-F, the efficiency-linearity tradeoff, PAPR back-off, AM-AM/AM-PM, ACLR, and linearization (DPD, feedforward, Doherty, load-pull) for RF interviews.

How mixer and frequency-conversion interviews test the image problem, image-reject vs IF filtering, conversion gain, NF, IIP2/IIP3, passive vs active mixers, and spurs.

ADC and DAC interview prep: sampling, quantization, SNR=6.02N+1.76 dB, ENOB, SFDR, INL/DNL, oversampling and sigma-delta, pipeline vs SAR vs flash, aperture jitter.

Phase noise & jitter interview prep: L(f) dBc/Hz vs RMS/pk-pk jitter, RJ vs DJ, integrated phase noise & EVM, reciprocal mixing, Leeson model, phase-noise-to-jitter conversion.

SerDes interview prep: NRZ vs PAM4, CDR/clock recovery, TX FFE/RX CTLE/DFE equalization, eye diagrams, BER, line coding, and PCIe/Ethernet lane rates.

PCIe Gen5 vs Gen6 for interviews: 32 GT/s NRZ vs 64 GT/s PAM4, 128b/130b vs FLIT + FEC, equalization, retimers, and channel reach.

DDR/LPDDR interview prep: double data rate, prefetch, banks and ranks, DQS source-synchronous strobing, read/write leveling, ODT termination, and DDR bus signal integrity.

Signal integrity interview prep: transmission lines, characteristic impedance, reflections, ISI, crosstalk, insertion/return loss, eye diagrams, and channel S-parameters.

Interview prep on power integrity and PDN design: target impedance, decoupling hierarchy, plane resonance, SSN/ground bounce, IR drop, and why PI and SI couple.

CDC interview prep: metastability and MTBF, two-flop synchronizers, Gray-code/handshake/async-FIFO for multi-bit, reconvergence hazards, and CDC/RDC verification.

Digital predistortion for PA linearization: inverse PA modeling, memory polynomials, indirect-learning adaptation, observation receivers, and ACLR/EVM trade-offs.

FIR vs IIR digital filter design for DSP interviews: stability, linear phase and group delay, windowing vs Parks-McClellan vs bilinear transform, and fixed-point effects.

Interview prep on the FFT and spectral analysis: DFT vs FFT, leakage and windowing, resolution vs zero-padding, scalloping, processing gain, OFDM and sensing.

Receiver AGC for engineering interviews: the detector/loop-filter/VGA feedback loop, log-domain control, attack/decay, ADC headroom, and burst vs continuous design.

RedCap (Reduced Capability / NR-Light) interview prep — Rel-17 mid-tier 5G IoT between eMBB and NB-IoT/LTE-M: 20 MHz FR1 cap, fewer Rx branches, HD-FDD, and Rel-18 eRedCap.

NR sidelink (PC5) and C-V2X for interviews — Mode 1 vs Mode 2, resource pools, NR Rel-16/17 vs LTE C-V2X, V2X use cases, relation to DSRC, and sidelink synchronization.

NB-IoT vs LTE-M (eMTC) for interviews: bandwidth, coverage enhancement and CE levels, PSM/eDRX power saving, mobility and voice, and migration into 5G with RedCap.

TSN interview prep: IEEE 802.1 deterministic Ethernet — 802.1AS time sync, Qbv time-aware shaper, Qbu preemption, CBS, and 5G-TSN integration.

Massive MIMO for wireless interviews: M ≫ K large arrays, channel hardening, TDD reciprocity CSI, pilot contamination, array vs multiplexing gain, and hybrid beamforming.

MU-MIMO vs SU-MIMO: who is served, where multiplexing happens, device antenna needs, CSIT, dominant gain, CSI-error sensitivity, and best-fit scenarios.

Analog vs digital vs hybrid beamforming: RF chains, phase-shifter vs baseband weighting, simultaneous streams, MU-MIMO, the ADC power wall, and mmWave vs sub-6 use.

Wi-Fi MU-MIMO vs OFDMA across 802.11ac/ax/be: spatial vs frequency multiplexing, downlink vs uplink, the Trigger frame, channel sounding, and how they combine.

OFDM vs OFDMA vs SC-FDMA: waveform vs multiple-access, PAPR trade-offs, why LTE uplink chose SC-FDMA, and why 5G NR uplink defaults to CP-OFDM.

FSM coding styles for interviews: one-hot vs binary vs gray state encoding, one/two/three-process RTL structure, Moore vs Mealy, and safe illegal-state recovery.

Reset strategies for RTL interviews: synchronous vs asynchronous reset, the async-assert/sync-deassert reset synchronizer, reset trees, multi-domain release ordering, and DFT interaction.

SDC constraints for interviews: create_clock and create_generated_clock, set_input_delay/set_output_delay, false paths vs asynchronous CDC, multicycle paths, and how SDC drives STA signoff.

Testbench architecture for RTL/verification interviews: self-checking testbenches, generator/driver/monitor/scoreboard structure, directed vs constrained-random stimulus, and functional coverage.

VHDL entities and architectures for interviews: the entity/architecture split, multiple architectures per entity, configuration declarations, component instantiation, generics, and VHDL's strict typing.

VHDL signals vs variables for interviews: scheduled vs immediate assignment, delta-cycle simulation semantics, the last-write-wins signal gotcha, and shared variables.

VHDL processes and concurrent statements for interviews: sensitivity lists, process(all), concurrent vs sequential signal assignment, latch inference, and clocked processes with rising_edge.

VHDL packages and libraries for interviews: IEEE std_logic_1164 and numeric_std, package declarations vs bodies, custom packages, and library vs use clauses.